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module foct_top(
clk_osc,reset,//晶振,复位
AD_controlling,//AD
rs232_rx,rs232_tx//uart
//Clkout1
//状态与指示灯
);
input clk_osc;//clk_osc=40M
input reset;
//output reg Clkout1;
output[5:0] AD_controlling;
input rs232_rx;
output rs232_tx;
/*
AD_controlling = {AD_dith,AD_mode,AD_oe,AD_pga,AD_rand,AD_shdn}
AD_pga <= 0; // 0: 2.25Vpp 1: 1.5Vpp
AD_rand <= 0; // 0: normal operation 1: xor
AD_mode <= 1; // 0: binary 1: 2's complement
AD_oe <= 0; // 0: enable
AD_shdn <= 0; // 0: normal operation 1: high impedance
AD_dith <= 0; // 1: enable internal dith
*/
// CLK
wire IBUFG_CLK;
wire CLK_OUT1;
wire CLK_OUT2;
wire CLK_OUT3;
IBUFG #(
.IOSTANDARD("DEFAULT")
) IBUFG_inst (
.O(IBUFG_CLK), // Clock buffer output
.I(clk_osc) // Clock buffer input (connect directly to top-level port)
);
//DCM
IPDCM instance_name1
(// Clock in ports
.CLK_OSCIN(IBUFG_CLK), // IN
// Clock out ports
.CLK_OUT1(CLK_OUT1), // OUT 40M
.CLK_OUT2(CLK_OUT2), // OUT 80M
.CLK_OUT3(CLK_OUT3), // OUT 50M
// Status and control signals
.RESET(reset)); // IN
// INST_TAG_END ------ End INSTANTIATION Template ---------
// UART
my_uart_top uart(
.clk(CLK_OUT2),
.rst_n(reset),
.rs232_rx(rs232_rx),
.rs232_tx(rs232_tx)
);
reg[5:0] AD_controlling;
always @(posedge CLK_OUT3)
begin
if (!reset)
AD_controlling <= 6'b110111;
else
AD_controlling <= 6'b001000;
end
reg [15:0] counter1,counter2,counter3;
always @(posedge CLK_OUT1 or negedge reset)
begin
if (!reset)
counter1 <= 16'h0000;
else if (counter1 <=16'h1000)
counter1 <= counter1+1;
else counter1 <=16'b1;
end
always @(posedge CLK_OUT3 or negedge reset)
begin
if (!reset)
counter2 <= 16'h0000;
else if (counter2 <=16'h1100)
counter2 <= counter2+1;
else counter2 <=16'b1;
end
//assign Clkout1 = CLK_OUT3;
endmodule
基本要求:倍频输出CLK_OUT1 40M;CLK_OUT2 50M; CLK_OUT3 80M;
软件版本:ISE14.6;
报如下错误:
ERROR:NgdBuild:770 - IBUFG 'IBUFG_inst' and IBUFG 'clkin1_buf' on net
'IBUFG_CLK' are lined up in series. Buffers of the same direction cannot be
placed in series.
ERROR:NgdBuild:462 - input pad net 'IBUFG_CLK' drives multiple buffers:
请教高手 ,怎么修改? |
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