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[招聘] [猎头]Fro-end ASIC Design CAD engineer & IC Design Verificat

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发表于 2013-9-8 17:28:20 | 显示全部楼层 |阅读模式

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Sr. Fro-end ASIC Design CAD engineer



Position Summary



?    Participate in the design and implementation of the leading edge, front-end ASIC design flow

?    Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge APU and GPU products

?    Technical support and programming

?    Interface with EDA vendors on technology







Sr. Fro-end ASIC Design CAD engineer



Essential Requirements/Qualifications:



1.    Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experience

2.    Experience in Front-end digital design and VerilogHDL is required

3.    Good programming skill with one or more languages (e.g. Tcl, Perl, python, c/c++, etc.) in Unix/Linux and a strong desire to automate flow

4.    Familiar with SRAM design and behaviour is a plus

5.    Familiar with one or more ASIC flows (logic synthesis, STA etc.) and usage of related EDA tools is a plus

6.    Good written and spoken English

7.    Good communication skills and be able to work both independently and in a team





MTS ASIC Design Verification Engineer - Video



SCBU APU Design Verification team is looking for highly motivated Verification Engineers to work on next generation APU SoC development.





KEY RESPONSIBILITIES:



-    Work closely with the SoC design team on understanding the APU system features being designed;

-    Develop and execute test plans for system level functional features related to Video Codec, Audio Processor, Display Port, Security, PCIe Controller;

-    Design, implement and improve verification testbench in Verilog, System-Verilog, C/C++, OVM;

-    Develop and refine test libraries, model and test cases;

-    Apply functional coverage/assertion into testbench as enhancement;

-    Support bring-up test plan and silicon validation for video IP/solutions;





REQUIREMENTS:



-    At least 5 years DV experience with good understanding on IP level verification and system level verification;

-    Deep knowledge of Video coding standards such as AVC, MVC, SVC, HEVC, MPEG4-2, VP8, MPEG-2, VC1 etc is a big plus;

-    Experience on Security, Memory Controller is preferred;

-    Experience with current verification methodologies (UVM, OVM, VMM...)

-    Experience using Perl or other UNIX scripting languages for flow automation

-    Good understanding on C/C++/Perl/Shell language;

-    Be fluent in English speaking and writing;







E-Mail: bestgrace@qq.com

QQ: 2043753191

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