在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 1416|回复: 0

[招聘] [猎头]ASIC DesignIPCore H.264 MPEG

[复制链接]
发表于 2013-9-5 20:39:11 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
ASIC DesignIPCore H.264 MPEG  
简历发bestgrace@qq.com  qq:2043753191





  

职位职能: 高级硬件工程师

职位描述:

Position Description:

The candidate will be the part of the design team for the development of next generation of video codec IP, the responsibilities include:

1.Micro-architecture definition;

2.Logic implementation with Verilog HDL;

3.Block-level verification;

4.Synthesis and pre-layout/post-layout timing closure;

5.Power analysis and reduction;

6.FPGA prototyping and debugging;

  

Qualification:

7.BS with 5+ years or MS with 2+ years experiences in electronic engineering/micro-electronics;

8.Expect elf-motivation and team player;

9.Solid skills and rich experiences in logic design, synthesis and timing analysis;

10.Hands-on engineering experiences in video codec development, familiar with video coding standard such like H.264/AVC, MPEG-4, AVS etc.;

11.Familiar with all front-end flows including LINT check, simulation, synthesis, STA, formal and power analysis, etc.;

12.Knowledge and experiences in Computer Architecture and RISC processor (ARM/MIPS/SPARC) micro-architecture would be a great plus;

13.Familiar with AXI4/AXI3 protocol, memory controller would be a plus;

14.Experience in FPGA prototyping and debugging would be a plush;

--
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条


小黑屋| 手机版| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-11-19 20:23 , Processed in 0.019299 second(s), 9 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表