Senior FPGA Engineer(内推)

jj_seu

职位描述：
1.FPGA design and verification. Porting asic code to FPGA platform, verify the whole design in FPGA system.
2.Lead the whole FPGA verification flow, include specification, coding, simulation, physical implementation and board level debugging.
2.Organize and Coordinate the work of debug team.
3.Capability of making rapidly scheme/method to trace issue.
4.RTL module development to assist the verification on FPGA

职位要求：
1.MS in Electronic or Computer Science Engineering is required. Expert in FPGA operation theory.
2.More than 4 years experience in design and verify on FPGA.
3.Project experience in mapping large scale, multi-million gate ASIC to multiple FPGAs
4.Architecture and design flow Expert in verilog or Vhdl. Familiar with FPGA EDA tools, such as Synplify, ISE, QuartusII Expert in Xilinx product.
5.Strong coding skills in Verilog/VHDL RTL.
6.Strong system bring up skills.
7.Experience in Chip and system test.
8.Analyze the FPGA requirement, evaluate the resource and select the chip type in the design phase.
9.Familiar with SOC architecture and OCP/AHB/APB.
10.Familiar with video system is preferable
11.The candidate is required to use the logic analyzer and oscillator to debug in FPGA Design.
12.Outstanding written and verbal communication skills in English
13.Willing to make travel abroad

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