Signal Integrity Characterization Techniques

eeicc

目录如下：
Part I: Getting Started – Introducing TDR and VNA Techniques and the Power of S-Parameters
Chapter 1: Signal-Port TDR, TDR/TDT, and Two-Port TDR: Interconnect Analysis is Simplified with
Physical Layer Tools
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
1.1: Introduction
1.2: Single-Port TDR
1.3: Two-Port TDR/TDT
1.4: Two-Port TDR/Crosstalk
1.5: Two-Port Differential TDR (DTDR)
Chapter 2: 4-Port TDR/VNA/PLTS – Interconnect Analysis Is Simplified with Physical Layer Test Tools
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
2.1: Introduction
2.2: Four-Port Techniques
2.3: Summary
Chapter 3: Differential Impedance Design and Verification with Time Domain Reflectometry
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Product Manager, Lightwave Division, Agilent Technologies
3.1: Abstract
3.2: Overview
3.3: Summary
Chapter 4: Utilizing TDR and VNA Data to Develop Four-Port Frequency-Dependent Models
Jim Mayrand, Signal Integrity Consultant
Mike Resso, Product Manager, Signal Integrity Operation, Agilent Technologies
Dima Smolyansky, TDA Systems
4.1: Abstract
4.2: Signal Integrity Challenges
4.3: Trend to Differential Topologies
4.4: Model Extraction Methodologies
4.5: Typical Four-Port Measurement Systems
4.6: Understanding Four-Port Mixed-Mode Analysis
4.7: Differential Interconnect Analysis
4.8: Measurement Accuracy and Error Correction
4.9: Design Case Study: Silicon Pipe Channel Plane
4.10: Frequency and Time Domain Analysis
4.11: Partitioning the Impedance Profile
4.12: Correlating Measurements and Models
4.13: HSpice Subcircuit Model for Backplane Only
4.14: Discontinuities: Flush Connector versus Cable Break
4.15: HSpice Subcircuit Model for Backplane Flush Connector
4.16: Model Optimization Schematic: Cable and Connector
4.17: Analyzing Connector Shunt Loss
4.18: Analyzing Fringe Capacitance
4.19: Modeled S-Parameters from Simulated TDR Waveforms
4.20: Modeled Eye Diagram with and without Connectors
4.21: Conclusion
Chapter 5: Accuracies and Limitations of Time and Frequency Domain Analyses of Physical-Layer
Devices
Robert Schaefer, Technical Leader and R&D Project Manager, Signal Integrity Group, Agilent
Technologies
5.1: Introduction
5.2: Equipment Setup
5.3: Fundamental Differences between TDR and VNA Instruments
5.4: TDR and VNA Sources
5.5: Architectures and Sources of Error
5.6: Calibration and Normalization
5.7: Measurement Accuracies: Reciprocity, Repeatability, and Drift
5.8: Measurement Comparisons
5.9: Summary
Chapter 6: Data Mining 12-Port S-Parameters
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test Division, Agilent Technologies
6.1: Abstract
6.2: High-Speed Serial Links and the Bandwidth of Interconnects
6.3: Four-Port S-Parameters
6.4: Twelve-Port S-Parameters and Information Overload
6.5: Serial-Link Performance Analysis
6.6: Losses
6.7: Impedance Continuities
6.8: Mode Conversion
6.9: Channel-to-Channel Crosstalk
6.10: Conclusion
Part II: Backplane Measurements and Analysis
Chapter 7: A Design of Experiments for Gigabit Serial Backplane Channels
Jack Carrel, System IO Specialist, Xilinx
Bill Dempsey, Owner and President, Redwire Enterprises
Mike Resso, Signal Integrity Application Scientist, Component Test Division, Agilent Technologies
7.1: Abstract
7.2: Introduction
7.3: Serial Backplane Channels
7.4: Backplane Platform Description
7.5: Daughtercard Description
7.6: Backplane Characterization
7.7: eHSD Connection Channels
7.8: HM-Zd Channels
7.9: HM-Zmm Channels
7.10: Crosstalk Measurements
7.11: Eye Diagram Analysis
7.12: Reference Channels
7.13: Summary
Chapter 8: Gigabit Backplane Design, Simulation, and Measurement: The Unabridged Story
Edward Sayre, Owner and Director, NESA
Jinhua Chen, Signal Integrity and EMI Engineer, NESA
Michael Baxter, Signal Integrity Engineer, NESA
Gautam Patel, Signal Integrity Engineer, New Product Development, Teradyne
John Goldie, Member of the Technical Staff, National Semiconductor
Mike Resso, Product Manager, Lightwave Division, Agilent Technologies
8.1: Introduction
8.2: Gigabit Backplane Design Case Study
8.3: Simulations
8.4: Measurements
8.5: Recommendations
8.6: Summary
Part III: Assuring Quality Measurements = Probing and De-Embedding
Chapter 9: The ABCs of De-Embedding
Eric Bogatin, President, Bogatin Enterprises
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
9.1: Introduction
9.2: Why De-Embedding?
9.3: Principles of De-Embedding
9.4: Obtaining the S-Parameter of the Fixture
9.5: Direct Measurement of Fixture S-Parameters
9.6: Building the Fixture S-Parameter by Fitting a Model to Measurement Data
9.7: Simulating the Fixture S-Parameter with a 3D Field Solver
9.8: Summary
Chapter 10: Backplane Differential Channel Microprobe Characterization in Time and Frequency
Domains
Eric Bogatin, Chief Technologial Officer, GigaTest Labs
Mike Resso, Signal Integrity Operation, Agilent Technologies
10.1: Abstract
10.2: Differential Channels Will Proliferate
10.3: The Bottleneck of SMAs
10.4: Advantages of Microprobing
10.5: Design for Test
10.6: Physical Layer Characterization
10.7: Understanding Four-Port Mixed-Mode Analysis
10.8: Design Case Study: XAUI Backplane
10.9: Comparing Time Domain and Frequency Domain Data
10.10: Coupling Pulls Down Differential Impedence
10.11: Eye Diagram Simulation Using Four-Port S-Parameters
10.12: Non-Ideal Differential Signaling (AKA Mode Conversion)
10.13: Summary
Chapter 11: Differential PCB Structures Using Measured TRL Calibration and Simulated Structure
De-Embedding
Heidi Barnes, High-Frequency Device Interface Board Designer, Verigy, Inc.
Antonio Ciccomancini, Application Engineer, CST of America, Inc.
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
Ming Tsai, Staff Hardware Development Engineer, Production Technology Division, Xilinx
11.1: Abstract
11.2: Introduction
11.3: Combined TRL Calibration and Simulated Structure De-Embedding for Multi-Mode N-Port
Systems
11.4: TRL Calibration Structures and Measurement Technique
11.5: Simulated Four-Port and 12-Port De-Embedding Structure
11.6: Device Structure under Test: Coupled and Un-Coupled via Pairs
11.7: Verification Using Four-Port Multimode TRL Calibration
11.8: Demonstration of the Combined TRL Calibration and Simulated Structure De-Embedding
Technique for Multi-Mode N-Port System
11.9: Summary and Conclusion
Chapter 12: Validating Transceiver FPGAs Using Advanced Calibration Techniques
Mike Resso, Business Development Manager, Signal Integrity Applications, Agilent Technologies
Hong Shi, Member of Technical Staff, Packing Technology, Altera
12.1: Abstract
12.2: Introduction
12.3: FPGA Applications Overview
12.4: Systematic Error Correction
12.5: Characterizing Differential Structures
12.6: Design Case Study
12.7: Conclusion
Chapter 13: Performance at the DUT: Techniques for Evaluating the Performance of an ATE System
at the DUT Socket
Heidi Barnes, Senior Application Consultant, Verigy
José Moreira, Senior Application Consultant, Verigy
Michael Comai, Senior Product Engineer, AMD
Abraham Islas, Senior Product Engineer, AMD
Francisco Tamayo-Broes, Product Development Engineer, AMD
Mike Resso, Signal Integrity Measurement Specialist, Component Test Division, Agilent
Technologies
Antonio Ciccomancini, Application Engineer, CST
Orlando Bell, Vice President, Engineering, GigaTest Labs
Ming Tsai, Principal Engineer, RF Design Group, Amalfi Semiconductor
13.1: Abstract
13.2: Introduction
13.3: Probing Technology, Interposer Design, and Mechanical Challenges
13.4: Calibration Techniques
13.5: Measuring the Probe and Probe Interposer Adapter
13.6: Test Fixture Performance Measurement
13.7: Focus Calibration on an ATE System: Measuring “at the DUT”
13.8: Conclusion
Chapter 14: Frequency Domain Calibration: A Practical Approach for the Serial Data Designer
Steven Corey, Principal Engineer, Electro-Optical Product Line, Tektronix
Eric Bogatin, President, Bogatin Enterprises
Dima Smolyansky, Product Marketing Manager, Tektronix
14.1: Abstract
14.2: Characterization of Serial Channels
14.3: Calibration Methods
14.4: Frequency Limits from Time Domain Measurements
14.5: Intrinsic Performance Limits
14.6: Variation in Typical Fixtures
14.7: Conclusion
Chapter 15: Practical Design and Implementation of Stripline TRL Calibration Fixtures for 10-Gigabit
Interconnect Analysis
Vince Duperron, Design Engineer, Molex
Dave Dunham, Electrical Engineer Manager, Molex
Mike Resso, Product Manager, Signal Integrity Applications, Agilent Technolgies
15.1: Abstract
15.2: Introduction
15.3: Why Calibrate?
15.4: Linear Two-Port Network Analyzer Measurements
15.5: VNA Measurement Errors
15.6: Vector Network Analyzer with Four Ports
15.7: A Real-World VNA Block Diagram Example: The Agilent N5230A-245
15.8: TRL Calibration Types
15.9: A Stripline TRL Fixture—A Design Case Study
15.10: The Macro Element View
15.11: Putting It Together
15.12: The Micro-Half of a TRL Design
15.13: Validation of TRL Fixtures
15.14: Using the Corrected Material Properties
15.15: Conclusion
Chapter 16: Channel Compliance Testing Utilizing Novel Statistical Eye Methodology
Anthony Sanders, Principal Engineer, Infineon
Mike Resso, Product Manager, Agilent Technologies
John D’Ambrosia, Manager, Semiconductor Relations, Tyco Electronics
16.1: Abstract
16.2: Introduction
16.3: StatEye Methodology
16.4: Cascading of Channel with Transmitter and Receiver Return Loss Model
16.5: Design Example Results
16.6: Conclusion
Chapter 17: Characterizing Jitter Performance on High-Speed Digital Devices Using Innovative
Sampling Technology
Osvaldo Buccafusca, Development Scientist, Lightwave Division, Agilent Technologies
Mike Resso, Product Manager, Agilent Technologies
17.1: Abstract
17.2: Introduction
17.3: Jitter Measurement
17.4: Random Sampling and Precision Time Base
17.5: Future Trends: Optical Sampling
17.6: Summary
Chapter 18: Signal Integrity Concerns When Modulating Laser Transmitters at Gigabit Rates
Stephen Reddy, Senior Design Engineer, Transmission Subsystems Group, JDS Uniphase
Laurie Taira, Senior Product Engineer, Research and Development, Delphi Connection Systems
Mike Resso, Product Manager, Lightwave Division, Agilent Technologies
Chapter 19: The Role of Dielectric Constant and Dissipation Factor Measurements in Multi-Gigabit
Systems
Eric Bogatin, President, Bogatin Enterprises
Shelley Begley, Team Leader, Agilent Technologies
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
19.1: Abstract
19.2: Introduction
19.3: Dielectric Properties of Laminates
19.4: Impact of Dielectic Materials in Signal Integration
19.5: Measurement Methods
19.6: Split-Post Dielectic Resonator Method
19.7: Conclusion
Chapter 20: Designing Scalable 10G Backplane Interconnect Systems Utilizing Advanced
Verification Methodologies
Kevin Grundy, Chief Executive Officer, SiliconPipe
Haw-Jyh Liaw, Director, Systems Engineering, Aeluros
Gary Otonari, Engineering Project Manager, GigaTest Labs
Mike Resso, Business Development Manager, Signal Integrity Operation, Agilent Technologies
20.1: Abstract
20.2: Approach
20.3: Current Design Impediments and Approaches
20.4: AE1002 Equalization
20.5: Improving the Channel
20.6: Initial Functional Testing
20.7: Full System Analysis
20.8: Summary
Chapter 21: Investigating Microvia Technology for 10 Gbps and Higher Telecommunications
Systems
Mike Resso, Business Development Manager, Signal Integrity Applications, Agilent Technologies
Thomas Gneiting, Founder, AdMOS Advanced Modeling
Roland M搀椀渀最攀爀, Senior Engineer, ERNI Electroapparate GmbH
Jason Roe, Application Engineer, ERNI Electroapparate GmbH
21.1: Abstract
21.2: Introduction
21.3: Telecom System Physical Layer Overview
21.4: Signal Integrity and Differential Signaling Backplane Data
21.5: Four Port Microvia Measurements
21.6: Microvia Construction
21.7: Modeling and Simulation Case Study
21.8: Summary and Conclusions
Chapter 22: ATE Interconnect Performance to 43 Gbps Using Advanced PCB Materials
Heidi Barnes, Senior Application Consultant, Verigy
José Moreira, Senior Application Consultant, Verigy
Tom McCarthy, Vice President, Taconic
William Burns, Senior Applications Engineer, Altanova Corporation
Crescencio Gutierrez, Engineering and Research and Development Manager, Harbor Electronics
Mike Resso, Signal Integrity Measurement Specialist, Agilent Technologies
22.1: Abstract
22.2: Introduction
22.3: Dielectic Materials for ATE Test Fixtures
22.4: The Taconic Fast-Rise Dielectic Materials
22.5: Experimental Results
22.6: Equalization to the Rescue
22.7: NEXT/FEXT Crosstalk Variations with PCB Materials
22.8: Dielectric Influence on Complex ATE Test-Fixture Stack-Up Decisions
22.9: Conclusion
Part VI: Future Directions
Chapter 23: Design and Test Challenges Facing Next-Generation 20 Gbps Interconnects
Jay Diepenbrock, Senior Technical Staff Member, Interconnect Qualification Engineering, IBM
Will Miller, Vice President, Engineering, Efficere Technologies
Mike Resso, Signal Integrity Applications Scientist, Component Test Division, Agilent Technologies
23.2: The Need to Measure Signal Integrity
23.3: Signal Integrity Analysis
23.4: High-Performance Test Figures
23.5: Test Fixtures: A User’s Perspective
23.6: Conclusion

eeicc

备注一下：全英文哦。

zhenningshen

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waveguides

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Jason.tschen

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hanks2007

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ztejoey

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yao487

回复 1# eeicc


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aniki804

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