【急招】SOC后端设计和验证(内部介绍)

jj_seu

- 参与IC设计布局布线, STA等环节的环境和流程维护
- 从事后端设计从netlist到GDSii的实现
- 编写相关脚本或约束，进行布局布线，时钟树生成，物理验证，功耗/电压降分析, 寄生参数提取等
- 产生并分析运行报告并给出解决方法

专业背景要求:
- 电子工程、计算机科学或相关学科本科3年、硕士3年以上工作经验
- 熟悉IC设计流程和常识，特别是当前流行的后端设计流程
- 熟练使用下面一种或几种EDA开发工具
- 擅长IC版图规划，电源规划，布局布线，时钟树生成、DRC/LVS经验者优先；有一些定制设计和模拟IP
使用经验者优先；有功耗分析电压降分析经验者优先；有串扰和信号完整性分析经验者优先
- 有90nm或65nm或.13工艺成功流片经历
综合素质要求:
- 良好的沟通能力和团队合作精神
- 高度的责任心和敬业精神
- 较强的逻辑思维能力，善于发现问题，具有良好的自学能力和解决问题的能力
- 英语熟练应用。
-本专业优先。
下面的职位要求，有其中之一最好没有也不强调：
1. Responsible for all aspects of physical design and implementation of integrated circuits and other asic.
2. Responsibilities include: Participating in the efforts in establishing CAD and physical design methodologies;
3. Focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology);
4, Chip floor plan; Power/clock distribution;
5. Chip assembly and P&R; Timing closure;
6. Power and noise analysis;
7. Back-end verification across multiple projects;

Requirements:
1. BSEE 5+years,MSEE 3+years experience in large VLSI physical design implementation;
2. Successful track record of delivering products to production is a must;
3. Understanding of custom Macro blocks such as RAMs, PLLs, high-speed IO drivers;
4. Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues;
5. Working knowledge of deep sub-micron routing issues as they relate to power and timing;
6. Circuit level comprehension of time critical paths. Spice experience a plus;
7. Should be a power user of Apollo/Astro for routing, PhysOpt (Physical Compiler) for placement, PrimeTime for Timing Verification, dc_shell etc.
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Apple
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
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