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有点复杂 ，不适合初学者，本大爷没仔细看，有兴趣的可以去研究，简介如下
ABSTRACT：
PLLs play an important role in modern high-speed designs, especially when configured for clock
tree insertion delay cancellation (IDC). Modeling the behavior of such PLLs accurately in
PrimeTime can be a challenge. This paper discusses basic modeling techniques for both standard
and multiplier IDC PLLs, duty cycle modeling, jitter and skew, and on-chip-variation effects. The
classic OCV/PLL excess pessimism problem will be explained and examined, and a couple of
workarounds will be discussed, including a novel new technique developed by the author. |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-7-23 11:23:24
