STA 静态时序分析急招 -简历发HR@hi-talent.net

jj_seu

http://blog.sina.com.cn/s/blog_6655477c0101g1yc.html

STA static Timing Analysis--简历发HR@hi-talent.net 集成电路IC设计/应用工程师

职位描述: * 6-8 years experience in Synthesis, STA and Timing closure activities of Full Chip and IPs * Experience in setting up full chip synthesis flow and develop synthesis constraints * Experience in STA and timing closure activities and coming up with STA constraints for the design. * Should be able to setup and own/drive the STA and timing closure activities for the design. * Experience with Synopsis DC & Synopsys Primetime tools and Primetime SI tools is required. * Experience with Cadence RC and ETS is a preferred. * The candidate should have very good knowledge about Architecture, RTL, Netlist and DFT methodology. * Should be able to write simple scripts to process the reports, come up with ECO etc., * Should understand the whole Physical Design flow and should be able to provide inputs for implementation * Should have timing closure experience for at least 2 full chip SoC designs. 职位描述: 服务于某知名的IC设计公司，负责实施从netlist 到GDS2的所有物理设计，包括floorplan, Powerplan, P&R, CTS, Physical verification、timing analysis、Power analysis等。 具体要求： 1．熟练掌握深亚微米后端物理设计流程者佳。 2．熟练使用Synopsys, Cadence或Magma等数字芯片物理设计工具；熟练使用Calibre等物理验证工具；熟练使用PT等时序验证工具者佳。 3．良好的沟通能力和团队合作能力。 4．本科以上学历，工作年限不限;微电子、电路、电子科学与技术等相关专业。 职位优势与机遇： 1、掌握 DFT 设计相关的整个流程，有机会了解整个后端流程。 2、作为高品质芯片供应商，在测试质量、成本方面，有更多挑战和发展的机遇 3、测试成本占芯片成本的比例不断增大，该职位有着广阔的发展前景 转正条件： Job Title: FullChip STA Engineer Location: Shanghai Department: Switching Requirement: One or more years of hands-on experience in macro level static timing analysis, fullchip static timing analysis. Proven track records of working independently on chip timing budgeting and fullchip timing closure Experience with Synopsys Synthesis and STA tools Good programming skill. Capable of writing Tcl or Perl. In-depth understanding of fabrication processing steps used in major fabrication industries. Self-motivated team worker, good verbal and written communication skills in English. Technical and team leadership proffered. Previous management experience highly desired. Experience with synthesis and DFT is preferred. 芯片STA验证 任职要求： 1、熟悉STA，对timing有理解，对.lib文件格式有一定了解； 2、本科以上学历，1年以上对PT时序分析经验； 3、富有研究精神，可以不断深入掌握工具及设计原理； 4、有良好的沟通能力和团队合作精神。 1. ASIC design flow, including synthesis, static timing analysis, formal verification and design for test. 2. IP design and integration Requirements: 1. BSEE or above 2. Experienced in frontend design of ASIC or FPGA chips 3. Experienced in one or more aspects in ASIC design flow: a. Logic synthesis b. STA c. Formal verification d. DFT -- MBIST,BSD,SCAN,TestKompress,ATPG,IP testing Job requirements/Responsibilities include: ·5+ years work experience in front end ASIC implementation methodology ·Strong understanding of synthesis flow using Design Compiler - for a low power (UPF) and high speed- complex SoC ·Hands on experience with formal verification tools such as LEC and/or formality ·Must have solid understanding of Clock Tree Synthesis using ICC ·Strong STA skills. Must have thorough knowledge on closing timing at unit and top level ·Ability to build new EDA-methodology-flow using perl, tcl and shell programming would be an added advantage Responsibilities: Design and integration DFT logic including SCAN, MBIST, JTAG Perform ATPG, simulation to sign off DFT Perform STA to sign off DFT timing Generate patterns for ATE and pattern support Requirements: BSEE or MSEE 3 to 7 years of experience in DFT field. Strong knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation. Experience with ATPG tools like TMAX, FASTSCAN a must Logic design and verification experience with knowledge of STA Programming in Perl, TCL and C++ is a plus Responsibilities: Design and integration DFT logic including SCAN, MBIST, JTAG Perform ATPG, simulation to sign off DFT Perform STA to sign off DFT timing Generate patterns for ATE and pattern support Requirements: BSEE or MSEE 1to 2 years of experience in DFT field. Strong knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation. Experience with ATPG tools like TMAX, FASTSCAN a must Logic design and verification experience with knowledge of STA Programming in Perl, TCL and C++ is a plus 1、 参与系统方案的时钟、复位、电源的布局规划；2、 负责从RTL质量检查、逻辑综合、形式验证、静态时序分析、功耗分析等工作；3、 配合物理设计团队实现芯片时序收敛，完成Signoff；任职要求：1、熟悉后端设计流程，从事过大型芯片后端设计的相关工作，熟悉后端设计工具；2、具备较强的思考问题，分析问题、解决问题的能力，较强的应变能力；3、有较好的英语听说读写能力，有海外学习工作经历佳。 贵司有招聘需求的，欢迎和我联系；如果你和你朋友有需要看工作机会的，发简历给我Jane-Jin@Hi-Talent.net Best Regards,ApplePrincipal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.上海芯相会企业管理咨询有限公司Mob:        15921265928Skype:      ScarlettJaneJinE-Mail:      Jane-Jin@Hi-Talent.netQQ:         1687562641Blog:       http://blog.sina.com.cn/u/1716864892Weibo:      http://weibo.com/u/1716864892Linkedin:    jj_seu@hotmail.com