verilog实现AD采样？

喜鹊王子 · 发表于 2013-7-14 18:32:32

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AD芯片输出支持SPI接口，现在想让AD芯片接到FPGA，让FPGA获取采样值并进行数据处理，AD芯片的接口如何用verilog来实现啊？有没有例子可以学习一下啊。

shiyinjita · 发表于 2013-7-15 22:20:48

FPGA模拟一个接口就可以了

zisa · 发表于 2013-7-18 11:58:15

Hi sir

I hope This code will help you

module spi_master_adc(
input SPI_MISO,
input CLKIN,
output reg AD_CONV,
output SPI_SCK,
output reg [27:0] ADC_DIGITAL,
output reg READY
);
parameter idle = 3'b001;
parameter convert = 3'b010;
parameter read = 3'b100;
reg [2:0] state= idle;
reg idle_count = 0;
reg [5:0] count=0;
reg [27:0] data;
initial
AD_CONV = 1;
// the clken signal control the clock signal sent to the adc.
// we want SPI_SCK for 33 clock cycles so we enable clken for only that duration of time.
assign SPI_SCK = CLKIN;
always@(posedge CLKIN)
begin
case(state)
idle : begin
// ready signal si set to zero to indicate output is not ready.
READY <= 0;
if(idle_count == 0) begin
// conversion is disabled
AD_CONV <= 1;
state <= idle;
idle_count <= idle_count + 1;
end
else begin
// reset the counting variable and goes to conversion state after 1 clock cycle
idle_count <= 0;
state <= convert;
end
end
convert: begin
READY <= 0;
// start the conversion process and enable the output clock.
AD_CONV <= 0;
if(count != 33)begin
// read the data only when the input isnot in high impedance state
if((count != 0) | (count != 1) | (count != 17) | (count != 33) ) begin
data <= data << 1;
data[0] <= SPI_MISO;
end
// updates the counter
end
else
begin
// after 33 cycles .. goes to read state
state <= read;
count <= 0;
end
count <= count + 1;
end
read : begin
// stops the output clock . stops the conversion and outputs the digital data.
count <= 0;
AD_CONV <= 0;
ADC_DIGITAL <= data;
READY <= 1;
// goesto idle state to start new conversion process.
state <= idle;
end
endcase
end
endmodule
and 2nd is
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 11:35:44 05/15/2010
// Design Name:
// Module Name: spi_master_amp
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi_master_amp(
input CLKIN, // CLOCK SOURCE FROM DCM (DIGITAL CLOCK MANAGER)
input RST,
input [7:0] GAIN_AB, // GAIN OF AMPLIFIER A AND B FROM MICROBLAZE
input ADC_DOUT, // PREVIOUS GAIN SERIAL INPUT FROM AMPIFIER
input WREN, // WRITE ENABLE FOR GAIN FROM MICROBLAZE
output reg AMP_CS, //CONTROL SIGNAL TO AMPLIFIER
output SPI_SCK, // CLOCK SIGNAL TO AMPLIFIER (10MHZ)
output reg SPI_MOSI, //SERIAL INPUT TO AMPLIFIER
output reg AMP_SHDN // RESET SIGNAL FOR AMPIFIER
);
reg [7:0] gain;
reg [3:0] count;
reg done = 0;
assign SPI_SCK = CLKIN;
always@(posedge CLKIN)
begin
if(RST)
AMP_SHDN <= 1;
else
begin
AMP_SHDN <= 0;
if(WREN) begin
gain <= GAIN_AB;
done <= 0;
end
else begin
{SPI_MOSI,gain} <= gain << 1;
if(count == 8) begin
done <= 1;
count <= 0;
end
else
count <= count + 1;
end
end
end
always@(negedge CLKIN)
begin
if(WREN | done)
AMP_CS <= 1;
else
AMP_CS <= 0;
end
endmodule

复制代码

[求助] verilog实现AD采样？

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