|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
得瑟的芯相会--新接的苏州工业园区职位-简历发HR@hi-talent.net
发信站: 水木社区 (Wed Jul 10 17:24:33 2013), 站内
只是心情好幽默一下，得瑟这个词，比得意好，瑟是瑟瑟发抖的意思呵呵，得瑟，就是也曾紧张的得瑟，也有曾高兴的得瑟的意思；
还有一段时间我受一个90后qq好友影响，高兴的时候说一句 我要杀人，崩溃的是也说一句我要杀人；但是真的不是要杀人，效果和我爱死你了差不多。
数字集成电路前端设计工程师Digital IC Frontend Design Engineer
Description:
1. Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
2. Write RTL code for high-speed and multi-clock domain designs.
3. Perform functional verification of designs on block and chip level.
4. Perform synthesis and pre-layout timing closure.
5. Perform the clock domain crossing analysis for the different products lines.
6. Generate the Timing .lib and ATPG package for the different product lines.
7. Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
1. MSEE with 2+ years.
2. Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
3. Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
4. Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
5. Understanding C and Perl programming.
6. Have a fluent oral and good writing English skill.
数字集成电路前端验证工程师 Digital IC Frontend Verification Engineer
Description:
l Develop and execute verification plan
l Develop and maintain verification environment
l Define and implement functional/code coverage plan
l Functional/code coverage analysis
l Run simulation for module and chip level, report and debug together with designer
l Develop/maintain/enhance environment (TB/tools/scripts/flow)
Requirement:
l MSEE with 2+ years.
l Proficient and experienced in SVA verification methodology
l Experienced with hardware verification language (Vera, Systems, SystemVerilog)
l Proficient with Verilog HDL
l Proficient with at least one scripting languages, e.g. Csh, Bash, Perl, Tcl
l Familiar with ASIC design flow
数字集成电路后端设计工程师 Digital IC Backend Design Engineer
Job Description:
· Digital layout design for blocks and chips;
· RTL synthesis and timing analysis;
· Documentation of design procedures;
· Work toward improving efficiency in design procedures and methodologies;
· Communicate effectively with other team members.
Requirements:
· Knowledge of IC design/EDA tools, technical documentation, utilities;
· Knowledge of Shell/Perl/Python script language programming skill in Unix/Linux environment;
· Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills;
· Bachelor degree in EE/CS;
· Good English skills to work in an English language environment.
数字集成电路前端设计高级工程师 Digital IC Frontend Design Engineer（Senior）
Description:
l Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
l Write RTL code for high-speed and multi-clock domain designs.
l Perform functional verification of designs on block and chip level.
l Perform synthesis and pre-layout timing closure.
l Perform the clock domain crossing analysis for the different products lines.
l Generate the Timing .lib and ATPG package for the different product lines.
l Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
l MSEE with 2+ years.
l Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
l Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
l Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
l Understanding C and Perl programming.
l Have a fluent oral and good writing English skill.
数字集成电路前端设计工程师 Digital IC Frontend Design Engineer
Description:
l Design and develop high-speed and low power digital circuits for the digital signal processing core of the different product lines including audio codec, ADC, PLL
l Write RTL code for high-speed and multi-clock domain designs.
l Perform functional verification of designs on block and chip level.
l Perform synthesis and pre-layout timing closure.
l Perform the clock domain crossing analysis for the different products lines.
l Generate the Timing .lib and ATPG package for the different product lines.
l Provide design documentation, information and support to customer application engineers and customers.
Qualifications:
l MSEE with 2+ years.
l Able to write RTL, run simulation, synthesis and timing closure, generate the ATPG package.
l Understanding the basic mixed-signal circuit including ADC, PLL, and audio codec.
l Able to perform functional and timing verification for circuit and logic design, know the SVA verification methodology and function coverage.
l Understanding C and Perl programming.
l Have a fluent oral and good writing English skill.
数字集成电路后端设计工程师 Digital IC Backend Design Engineer
Job Description:
· Digital layout design for blocks and chips;
· RTL synthesis and timing analysis;
· Documentation of design procedures;
· Work toward improving efficiency in design procedures and methodologies;
· Communicate effectively with other team members.
Requirements:
· Knowledge of IC design/EDA tools, technical documentation, utilities;
· Knowledge of Shell/Perl/Python script language programming skill in Unix/Linux environment;
· Has strong desires to learn and explore new technologies and demonstrates good analysis and problem-solving skills;
· Bachelor degree in EE/CS;
· Good English skills to work in an English language environment.
实际工作地点：苏州
贵司有招聘需求的，欢迎和我联系；
如果你和你朋友有需要看工作机会的，发简历给我Jane-Jin@Hi-Talent.net
Best Regards,
Jane.Jin 金娟
Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.
上海芯相会企业管理咨询有限公司
Mob: 15921265928
Skype: ScarlettJaneJin
E-Mail: Jane-Jin@Hi-Talent.net
QQ: 1687562641
Blog: http://blog.sina.com.cn/u/1716864892
Weibo: http://weibo.com/u/1716864892
Linkedin: jj_seu@hotmail.com |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-7-10 17:42:10
