SoC Encounter经典实例教程+代码

renrensd

好东西谢了。

jaja65

多謝樓主

Quinn714

回复 1# 胡兵

tudecheng

多谢分享

sky_k

感谢楼主分享，希望可以用到！

wanhi

非常感谢你

wenbow512512

学习一下

yuweilian

9.1之前的版本
ion
XOR2X1, XNOR2X1 2-input XOR and XNOR
TIELO, TIEHI Cells used to tie inputs to logic 1 or 0
OAI22X1, OAI21X1 OR-AND-Invert gates with 4 (22) and 3 (21) inputs
NOR3X1, NOR2X2, NOR2X1 2- and 3-input NOR
NAND3X1, NAND2X2, NAND2X1 2- and 3-input NAND
MUX2X2, MUX2NX1 2-input MUX, and 2-input inverting mux (N)
LCX1, LCNX1 Gated latches
INVX1, INVX2, INVX4, INVX8, INVX16 Inverters
FILL8, FILL4, FILL2, FILL Filler cells of various widths
These are used to fill empty spots in standard cell rows
ENINVX1, ENINVX2 Enabled inverters (tri-state inverters)
DCX1, DCNX1, DCBX1, DCBNX1 Edge triggered flip-flops
BUFX8, BUFX4, BUFX2 non-inverting buffers
AOI22X1, AOI21X1 AND-OR-Invert gates with 4 (22) and 3 (21) inputs
AND3X1 3-input AND
Figure 13.1: Cells contained in the UofU Digital v1 2 cell library. The cell names are coded
with output drive strengths: X1 is unit drive strength, and Xn is n-times that unit drive
strength. Sequential cells are coded with a C if they have a clear signal, B if they have
both Q and Qbar outputs, and N if they are clocked on a negative edge or level

goouy

感謝樓主分享

songzhihe66

学习了  谢谢