Help: how to set input slew for UMC 0.3um 1.8v for synopsys .lib?

wilson168

Recently, I got a task to calculate the synopsys .lib 7x7 timing model for UMC 0.3um 1.8v ?I am not sure how to set the input slew for all standard library cells.
For 5V condition, the range of input slew from 0.001ns to 4.7ns.
Can someone tech me how to set the proper input slew table?

phoenixson

rc_slew_upper_threshold_pct_fall
rc_slew_upper_threshold_pct_rise
rc_slew_lower_threshold_pct_fall
rc_slew_lower_threshold_pct_rise

wilson168

回复 2# phoenixson

Thank you.I exactly want to know the value of following parameters (in SiliconSmart) :
set smallest_slew ????
set largest_slew  ????

phoenixson

oh, i see, you can refer to the one of tsmc .13um. then after characterization, check value of each cell, if the result value is out of the range ,or  it 's not reasonable, then adjust the slew range accordingly.

wilson168

回复 4# phoenixson

Thanks for your input.It might take long time for all cells characterization and then to adjust the rang of input slew.
Is there any simple rule to decide those data according to voltage as well as temperature?
(If I have 5V condition as reference)

phoenixson

the best method is to check the other lib of of UMC 0.3um, of course , supply voltage should be  key  factor to input slew index, but i have no empiric value for it.

wilson168

回复 6# phoenixson


Thanks Sir,
Yes you are right. It might be the best way to reference other process node's setting.
All combination cells are no problem.
But for Flip-Flop cells with clear/reset pin are difficult to characterize.

papertiger

这个应该在后端设计里面讨论。

简单说，没有特别的规则如何设置transition time.
一般来说，通过工艺和应用。

工艺就是spice 仿真后多大了就误差太大，因为TLU必然有精度的损失，
找一个可接受的精度。

从应用上就是看0.3um 大多跑多少频率，比如跑100MHZ，那么一个时钟就是10ns，
最多不会超过5ns的transition。一般会设置在3.5-5ns 之间。

这个应该是fab 该做的。问fab 最好。

wilson168

回复 8# papertiger

Thanks for your point. It is great.Would you please show me a hspice simulation circuit which can measure the max frequency
for certain process node?

hendrix

能共享下库不