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发表于 2005-12-6 23:46:32
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Digital Logic and Microprocessor Design With VHDL
Chapter 1 Designing Microprocessors
1.1Overview of a Microprocessor3
1.2Design Abstraction Levels6
1.3Examples of a 2-to-1 Multiplexer6
1.3.1Behavioral Level7
1.3.2Gate Level8
1.3.3Transistor Level9
1.4Introduction to VHDL9
1.5Synthesis12
1.6Going Forward12
1.7Summary Checklist13
1.8Problems13
Chapter 2 Digital Circuits
2.1Binary Numbers3
2.2Binary Switch5
2.3Basic Logic Operators and Logic Expressions6
2.4Truth Tables7
2.5Boolean Algebra and Boolean Function8
2.5.1Boolean Algebra8
2.5.2* Duality Principle10
2.5.3Boolean Functions and their Inverses10
2.6Minterms and Maxterms13
2.6.1Minterms14
2.6.2* Maxterms15
2.7Canonical, Standard, and non-Standard Forms17
2.8Logic Gates and Circuit Diagrams17
2.9Designing a Car Security System20
2.10VHDL for Digital Circuits22
2.10.1VHDL code for a 2-input NAND gate22
2.10.2VHDL code for a 3-input NOR gate23
2.10.3VHDL code for a function24
2.11Summary Checklist25
2.12Problems26
Chapter 3 Combinational Circuits
3.1Analysis of Combinational Circuits3
3.1.1Using a Truth Table3
3.1.2Using a Boolean Function6
3.2Synthesis of Combinational Circuits7
3.3* Technology Mapping9
3.4Minimization of Combinational Circuits12
3.4.1Karnaugh Maps12
3.4.2Don’t-cares17
3.4.3* Tabulation Method18
3.5* Timing Hazards and Glitches19
3.5.1Using Glitches21
3.6BCD to 7-Segment Decoder21
3.7VHDL for Combinational Circuits23
3.7.1Structural BCD to 7-Segment Decoder24
3.7.2Dataflow BCD to 7-Segment Decoder28
3.7.3Behavioral BCD to 7-Segment Decoder28
3.8Summary Checklist30
3.9Problems31
Chapter 4 Standard Combinational Components
4.1Signal Naming Conventions3
4.2Adder3
4.2.1Full Adder3
4.2.2Ripple-carry Adder5
4.2.3* Carry-lookahead Adder6
4.3Two’s Complement Binary Numbers7
4.4Subtractor9
4.5Adder-Subtractor Combination11
4.6Arithmetic Logic Unit13
4.7Decoder18
4.8Encoder20
4.8.1* Priority Encoder21
4.9Multiplexer21
4.9.1* Using Multiplexers to Implement a Function24
4.10Tri-state Buffer24
4.11Comparator26
4.12Shifter29
4.12.1* Barrel Shifter31
4.13* Multiplier31
4.14Summary Checklist33
4.15Problems34
Chapter 5 Implementation Technologies
5.1Physical Abstraction3
5.2Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)4
5.3CMOS Logic5
5.4CMOS Circuits6
5.4.1CMOS Inverter6
5.4.2CMOS NAND Gate7
5.4.3CMOS AND Gate8
5.4.4CMOS NOR and OR Gates10
5.4.5Transmission Gate10
5.4.62-input Multiplexer CMOS Circuit10
5.4.7CMOS XOR and XNOR Gates12
5.5Analysis of CMOS Circuits13
5.6* Using ROMs to Implement a Function14
5.7* Using PLAs to Implement a Function16
5.8* Using PALs to Implement a Function20
5.9* Complex Programmable Logic Device (CPLD)22
5.10* Field Programmable Gate Array (FPGA)24
5.11Summary Checklist25
5.12Problems25
Chapter 6 Latches and Flip-Flops
6.1Bistable Element3
6.2SR Latch4
6.3SR Latch with Enable6
6.4D Latch7
6.5D Latch with Enable8
6.6Clock9
6.7D Flip-Flop10
6.7.1* Alternative Smaller Circuit11
6.8D Flip-Flop with Enable12
6.9Asynchronous Inputs13
6.10Description of a Flip-Flop14
6.10.1Characteristic Table14
6.10.2Characteristic Equation14
6.10.3State Diagram15
6.10.4Excitation Table15
6.11* Timing Issues15
6.12Car Security System—Version 216
6.13VHDL for Latches and Flip-Flops17
6.13.1Implied Memory Element17
6.13.2VHDL Code for a D Latch with Enable18
6.13.3VHDL Code for a D Flip-Flop18
6.13.4VHDL Code for a D Flip-Flop with Enable and Asynchronous Set and Clear21
6.14* Other Flip-Flop Types22
6.14.1SR Flip-Flop22
6.14.2JK Flip-Flop23
6.14.3T Flip-Flop24
6.15Summary Checklist25
6.16Problems25
Chapter 7 Sequential Circuits
7.1Finite State Machine (FSM) Models3
7.2State Diagrams5
7.3Analysis of Sequential Circuits8
7.3.1Excitation Equation9
7.3.2Next-state Equation9
7.3.3Next-state Table9
7.3.4Output Equation10
7.3.5Output Table10
7.3.6State Diagram11
7.3.7Analysis of a Moore FSM11
7.3.8Analysis of a Mealy FSM13
7.4Synthesis of Sequential Circuits15
7.4.1State Diagram15
7.4.2Next-state Table16
7.4.3Implementation Table18
7.4.4Excitation Equation and Next-state Circuit19
7.4.5Output Table and Equation19
7.4.6FSM Circuit19
7.4.7Synthesis of Moore FSMs19
7.4.8Synthesis of a Mealy FSM25
7.5Unused State Encodings and the Encoding of States27
7.6Designing a Car Security System—Version 330
7.7VHDL for Sequential Circuits31
7.8* Optimization for Sequential Circuits37
7.8.1State Reduction37
7.8.2State Encoding38
7.8.3Choice of Flip-Flops39
7.9Summary Checklist42
7.10Problems42
Chapter 8 Standard Sequential Components
8.1Registers3
8.2Shift Registers5
8.2.1Serial-to-Parallel Shift Register5
8.2.2Serial-to-Parallel and Parallel-to-Serial Shift Register7
8.3Counters9
8.3.1Binary Up Counter10
8.3.2Binary Up-down Counter12
8.3.3Binary Up-down Counter with Parallel Load14
8.3.4BCD Up Counter15
8.3.5BCD Up-down Counter16
8.4Register Files18
8.5Static Random Access Memory22
8.6* Larger Memories26
8.6.1More Memory Locations26
8.6.2Wider Bit Width26
8.7Summary Checklist29
8.8Problems29
Chapter 9 Datapaths
9.1Designing Dedicated Datapaths4
9.1.1Selecting Registers7
9.1.2Selecting Functional Units8
9.1.3Data Transfer Methods9
9.1.4Generating Status Signals10
9.2Using Dedicated Datapaths11
9.3Examples of Dedicated Datapaths11
9.3.1Simple IF-THEN-ELSE12
9.3.2Counting 1 to 1013
9.3.3Summation of n Down to 115
9.3.4Factorial of n16
9.3.5Count 0’s and 1’s18
9.4General Datapaths20
9.5Using General Datapaths21
9.6A More Complex General Datapath23
9.7Timing Issues27
9.8VHDL for Datapaths29
9.8.1Dedicated Datapath29
9.8.2General Datapath30
9.9Summary Checklist35
9.10Problems35
Chapter 10 Control Units
10.1Constructing the Control Unit4
10.1.1Counting 1 to 104
10.1.2Simple IF-THEN-ELSE8
10.2Generating Status Signals14
10.3Stand-Alone Controllers22
10.3.1Rotating Lights22
10.3.2PS/2 Keyboard Controller26
10.3.3VGA Monitor Controller30
10.4* ASM Charts and State Action Tables41
10.4.1ASM Charts41
10.4.2State Action Tables44
10.5VHDL for Control Units45
10.6Summary Checklist46
10.7Problems48
Chapter 11 Dedicated Microprocessors
11.1Manual Construction of a Dedicated Microprocessor4
11.2Examples of Manual Designs for Dedicated Microprocessors8
11.2.1Greatest Common Divisor8
11.2.2Summing Input Numbers15
11.2.3High-Low Guessing Game20
11.2.4Finding the Largest Number26
11.3VHDL for Dedicated Microprocessors32
11.3.1FSM + D Model32
11.3.2FSMD Model37
11.3.3Behavioral Model39
11.4Summary Checklist40
11.5Problems40
Chapter 12 General-Purpose Microprocessors
12.1Overview of the CPU Design3
12.2The EC-1 General-Purpose Microprocessor4
12.2.1Instruction Set4
12.2.2Datapath5
12.2.3Control Unit6
12.2.4Complete Circuit10
12.2.5Sample Program11
12.2.6Simulation13
12.2.7Hardware Implementation13
12.3The EC-2 General-Purpose Microprocessor14
12.3.1Instruction Set14
12.3.2Datapath15
12.3.3Control Unit16
12.3.4Complete Circuit19
12.3.5Sample Program20
12.3.6Hardware Implementation22
12.4VHDL for General-Purpose Microprocessors23
12.4.1Structural FSM+D23
12.4.2Behavioral FSMD30
12.5Summary Checklist33
12.6Problems33
Appendix A Schematic Entry Tutorial 1
A.1Getting Started2
A.1.1Preparing a Folder for the Project2
A.1.2Starting MAX+plus II2
A.1.3Starting the Graphic Editor3
A.2Using the Graphic Editor4
A.2.1Drawing Tools4
A.2.2Inserting Logic Symbols4
A.2.3Selecting, Moving, Copying, and Deleting Logic Symbols5
A.2.4Making and Naming Connections6
A.2.5Selecting, Moving and Deleting Connection Lines8
A.3Specifying the Top-Level File and Project8
A.3.1Saving the Schematic Drawing8
A.3.2Specifying the Project8
A.4Synthesis for Functional Simulation8
A.5Circuit Simulation9
A.5.1Selecting Input Test Signals9
A.5.2Customizing the Waveform Editor10
A.5.3Assigning Values to the Input Signals11
A.5.4Saving the Waveform File11
A.5.5Starting the Simulator12
A.6Creating and Using the Logic Symbol13
Appendix B VHDL Entry Tutorial 2
B.1Getting Started2
B.1.1Preparing a Folder for the Project2
B.1.2Starting MAX+plus II2
B.1.3Creating a Project3
B.1.4Editing the VHDL Source Code4
B.2Synthesis for Functional Simulation4
B.3Circuit Simulation5
B.3.1Selecting Input Test Signals5
B.3.2Customizing the Waveform Editor7
B.3.3Assigning Values to the Input Signals8
B.3.4Saving the Waveform File8
B.3.5Starting the Simulator8
Appendix C UP2 Programming Tutorial 3
C.1Getting Started2
C.1.1Preparing a Folder for the Project2
C.1.2Creating a Project3
C.1.3Viewing the Source File3
C.2Synthesis for Programming the PLD4
C.2.1Selecting the Target Device4
C.2.2Synthesis4
C.3Circuit Simulation5
C.4Maping the I/O Pins with the Floorplan Editor7
C.5Fitting the Netlist and Pins to the PLD9
C.6Hardware Setup10
C.6.1Installing the ByteBlaster Driver10
C.6.2Jumper Settings10
C.6.3Hardware Connections10
C.7Programming the PLD11
C.8Testing the Hardware13
C.9MAX7000S EPM7128SLC84-7 Summary13
C.9.1JTAG Jumper Settings14
C.9.2Prototyping Resources for Use14
C.9.3General Pin Assignments15
C.9.4Two Push-Button Switches15
C.9.516 DIP Switches15
C.9.616 LEDs16
C.9.77-Segment LEDs16
C.9.8Clock16
C.10FLEX10K EPF10K70RC240-4 Summary17
C.10.1JTAG Jumper Settings17
C.10.2Prototyping Resources for Use17
C.10.3Two Push-Button Switches17
C.10.48 DIP Switches17
C.10.57-Segment LEDs18
C.10.6Clock18
C.10.7PS/2 Port18
C.10.8VGA Port18
Appendix D VHDL Summary
D.1Basic Language Elements2
D.1.1Comments2
D.1.2Identifiers2
D.1.3Data Objects2
D.1.4Data Types2
D.1.5Data Operators5
D.1.6ENTITY6
D.1.7ARCHITECTURE6
D.1.8GENERIC7
D.1.9PACKAGE9
D.2Dataflow Model Concurrent Statements10
D.2.1Concurrent Signal Assignment10
D.2.2Conditional Signal Assignment10
D.2.3Selected Signal Assignment11
D.2.4Dataflow Model Sample11
D.3Behavioral Model Sequential Statements12
D.3.1PROCESS12
D.3.2Sequential Signal Assignment12
D.3.3Variable Assignment12
D.3.4WAIT13
D.3.5IF THEN ELSE13
D.3.6CASE13
D.3.7NULL14
D.3.8FOR14
D.3.9WHILE14
D.3.10LOOP15
D.3.11EXIT15
D.3.12NEXT15
D.3.13FUNCTION15
D.3.14PROCEDURE16
D.3.15Behavioral Model Sample17
D.4Structural Model Statements17
D.4.1COMPONENT Declaration18
D.4.2PORT MAP18
D.4.3OPEN19
D.4.4GENERATE19
D.4.5Structural Model Sample19
D.5Conversion Routines21
D.5.1CONV_INTEGER()21
D.5.2CONV_STD_LOGIC_VECTOR(,)21
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