设计中用了两个DDR2颗粒,调试时用一个颗粒调试能够通过,但是两个颗粒合在一个工程中总是Fitter报错,如下所示:Error (176414): Can't place node ddr2_app_intf:ddr2_app_intf_a_inst|ddr2_intf:ddr2_intf_inst|ddr2_intf_controller_phy:ddr2_intf_controller_phy_inst|ddr2_intf_phy:ddr2_intf_phy_inst|ddr2_intf_phy_alt_mem_phy:ddr2_intf_phy_alt_mem_phy_inst|ddr2_intf_phy_alt_mem_phy_clk_reset:clk|ddio_mimic in DDIOINCELL_X98_Y96_N4 due to I/O or LAB clock region constraints
Extra Info (171053): Can't globally route 1 more signal(s) into a region -- 9 global signals have been allocated to the region but the hardware only allows 9 global signals