|
|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
In Chapter 2, fundamental limitations to the power dissipation in CMOS A/D
converters are discussed by examining implementation issues on three key functions,
sampling, quantization, and reference generation. Practical issues are also briefly
discussed.
4
In Chapter 3, several high speed CMOS A/D converter architectures are reviewed.
First, a flash A/D architecture is presented and its limitations are studied. Then, an attempt
is made to present how ADC architectures have evolved to reduce power and area from
the power dissipation point of view.
In Chapter 4, the pipeline architecture is presented in more detail from its basic
operation to actual implementation of each pipeline stage.
In Chapter 5, techniques to reduce the power and to allow low-voltage operation of
the pipeline architecture are presented.
An experimental prototype A/D converter has been fabricated, and its
measurement results are presented in Chapter 6 along with discussions on key
performances.
Finally, the conclusion is presented in Chapter 7. |
|
/1 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2007-1-17 19:47:58
楼主
