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最新十号补丁，2013年5月24号发布。共36个包，下载安装即可
已经破解的同学，需要安装后重新破解。方法同原来一样。
- G6 G& \- O" E; RDATE: 05-24-2013 HOTFIX VERSION: 010
1 Y4 H2 Q6 o I5 Q6 h! h( a===================================================================================================================================5 y0 ?0 l+ l y' I$ z3 g
CCRID PRODUCT PRODUCTLEVEL2 TITLE0 Y) R3 v' }$ p8 W* S/ `8 b* g# S: W
=================================================================================================================================== s& W: d/ m0 ] U; e# |
1084716 ALLEGRO_EDITOR OTHER Getting an MPS error when updating CM from SigXplorer
& a' [$ T8 O0 u( Q4 U# {1111430 FSP CAPTURE_SCHEMATI Auto-resize the schematic sheet so that hierarchical block fits within border
5 n6 X( N% ^- N" f) ?4 t0 z7 c7 d8 i, Z5 O1119007 CONCEPT_HDL CORE PDF Publish of schematic creates extremely large PDF files# M/ q8 A7 E3 s6 H% y) |
1121020 FSP MODEL_EDITOR Cut-Paste from Excel causes empty cell in Rule Editor
2 B4 A- ~% }! h/ V- F1124610 PSPICE SIMULATOR Attached design gives "INTERNAL ERROR -- Overflow" in SPB116.6" V- G' R$ {1 D* j$ |/ l* n" ~3 p: F
1125330 FSP CAPTURE_SCHEMATI FSP generates OrCAD schematics with components (Resistors) outside page border( k- A6 E6 L6 @* U) V
1131775 ADW LRM LRM error with local libs & TDA
6 E9 H! X9 V% w; W: N4 N. D. s1131868 CONCEPT_HDL CONSTRAINT_MGR Many net-class constraints "fell off" the design after uprev and Import Design of GEP46 [, T- U( @' ^
1132080 ALLEGRO_EDITOR PLOTTING Size of the logo changes after File > Import > Logo9 d3 h2 ^, L/ S* x8 ]
1134956 SPECCTRA HIGHSPEED Route Automatic fails with error when Impedance rules are turned ON in Allegro CM.
6 d: _" \0 O8 u. f1135548 SIP_LAYOUT SHAPE This design shows two areas with shape shorting errors that should not occur
5 F5 ], I, `" i' H. c+ _1138312 ALLEGRO_EDITOR MANUFACT NCROUTE is not generated for filled rectangle slot ?8 {/ p! R4 m3 S5 O
1139433 ALLEGRO_EDITOR GRAPHICS embedded netnames not displayed or getting very small upon panning after exiting 3D Viewer.; T7 d' B; c/ i. C ]5 s1 S! v* T( _ W
1139509 CONCEPT_HDL CORE The LRM update changes npn device to resistor: K W+ P# l& V0 X
1140752 ALLEGRO_EDITOR PLACEMENT Moving a place replicate module crashes allegro
+ _% I# d7 v j: `6 ?7 `3 E1141314 SIP_LAYOUT SYMB_EDIT_APPMOD Design will lock up after changing the border using Edit Boundary in Symbol edior mode.
9 H. ^$ [: |) B; l1 y1 a1141751 ALLEGRO_EDITOR INTERFACES Allegro Crashes with Export IPC2581.
0 w I, U: D; A3 W, P, w1142478 CONSTRAINT_MGR INTERFACE_MAPPER adding constraint to netgroup causes CM & PCB SI to crash5 e1 m0 D+ k4 T8 [: F; S c. y
1142884 ALLEGRO_EDITOR OTHER Boolean type user defined property doesn't export to the PDF
+ g: j2 D- i1 J7 g9 b3 @1143199 SIP_LAYOUT DIE_EDITOR Enable bump remastering* k B g& T5 s( F( }4 V3 l' `
1143654 SIP_LAYOUT DIE_EDITOR Add X&Y offset when adding or moving a pin in die editor7
Hotfix_SPB16.60.010_wint_1of1.part01.rar
(15 MB, 下载次数: 145 )
Hotfix_SPB16.60.010_wint_1of1.part02.rar
(15 MB, 下载次数: 130 )
Hotfix_SPB16.60.010_wint_1of1.part03.rar
(15 MB, 下载次数: 113 )
Hotfix_SPB16.60.010_wint_1of1.part04.rar
(15 MB, 下载次数: 105 )
Hotfix_SPB16.60.010_wint_1of1.part05.rar
(15 MB, 下载次数: 106 )
Hotfix_SPB16.60.010_wint_1of1.part06.rar
(15 MB, 下载次数: 97 )
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2013-5-29 09:56:07
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