output StateIdle; // Idle state
output StateIPG; // IPG state
output StatePreamble; // Preamble state
output [1:0] StateData; // Data state
output StatePAD; // PAD state
output StateFCS; // FCS state
output StateJam; // Jam state
output StateJam_q; // Delayed Jam state
output StateBackOff; // Backoff state
output StateDefer; // Defer state
output StartFCS; // FCS state will be activated in next clock
output StartJam; // Jam state will be activated in next clock
output StartBackoff; // Backoff state will be activated in next clock
output StartDefer; // Defer state will be activated in next clock
output DeferIndication;
output StartPreamble; // Preamble state will be activated in next clock
output [1:0] StartData; // Data state will be activated in next clock
output StartIPG; // IPG state will be activated in next clock
wire StartIdle; // Idle state will be activated in next clock
wire StartPAD; // PAD state will be activated in next clock
// This sections defines which interpack gap rule to use
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
Rule1 <= #Tp 1'b0;
else
begin
if(StateIdle | StateBackOff)
Rule1 <= #Tp 1'b0;
else
if(StatePreamble | FullD)
Rule1 <= #Tp 1'b1;
end
end