状态机设计的经典资料byClifford E. Cummings

wice3

Abstract
This paper details proven RTL coding styles for efficient and synthesizable Finite State Machine (FSM)
design using IEEE-compliant Verilog simulators. Important techniques related to one and two always block
styles to code FSMs with combinational outputs are given to show why using a two always block style is
preferred. An efficient Verilog-unique onehot FSM coding style is also shown. Reasons and techniques for
registering FSM outputs are also detailed. Myths surrounding erroneous state encodings, full-case and
parallel-case usage are also discussed. Compliance and enhancements related to the IEEE 1364-2001
Verilog Standard, the proposed IEEE 1364.1 Verilog Synthesis Interoperability Standard and the proposed
Accellera SystemVerilog Standard are also discussed.

veno

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fhyfbjl

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haoziliao

alias

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wusuowei232

thanks very much

yangfunc

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alias

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alias

呵呵，受益非浅

risccpu

good, thanks