ISE 14.1 MAP ERROR

zongkai2003

ERRORlace:866 - Not enough valid sites to place the following IOBs:
   IO Standard: Name = LVCMOS25, VREF = NR, VCCO = 2.50, TERM = NONE, DIR =
   BIDIR, DRIVE_STR = 12
    IO
    IO_x
第一次用PlanAhead，不怎么会用，不过引脚约束什么是跟着语法自己写的。如下：


#Created by Constraints Editor (xc6slx45-csg324-3) - 2013/05/06
NET "clk" TNM_NET = "clk";
TIMESPEC TS_clk = PERIOD "clk" 20 MHz HIGH 50 %;
NET "cam_x_pclk" TNM_NET = "cam_x_pclk";
TIMESPEC TS_cam_x_pclk = PERIOD "cam_x_pclk" 27 MHz HIGH 50 %;
NET "cam_y_pclk" TNM_NET = "cam_y_pclk";
TIMESPEC TS_cam_y_pclk = PERIOD "cam_y_pclk" 27 MHz HIGH 50 %;
NET "clk" LOC = D11;
# CAM X Pin assign
NET "cam_x_pclk" LOC = T9;
NET "cam_x_mclk" LOC = V9;
NET "cam_x_vsync" LOC = T6;
NET "cam_x_hsync" LOC = V6;
#NET "cam_x_href" LOC = M8;
NET "cam_x_d[0]" LOC = M8;
NET "cam_x_d[1]" LOC = N8;
NET "cam_x_d[2]" LOC = U8;
NET "cam_x_d[3]" LOC = V8;
NET "cam_x_d[4]" LOC = U7;
NET "cam_x_d[5]" LOC = V7;
NET "cam_x_d[6]" LOC = N7;
NET "cam_x_d[7]" LOC = P8;
# CAM Y Pin assign
NET "cam_y_pclk" LOC = R10;
NET "cam_y_mclk" LOC = T10;
NET "cam_y_vsync" LOC = N9;
NET "cam_y_hsync" LOC = U11;
#NET "cam_y_href" LOC = M8;
NET "cam_y_d[0]" LOC = N11;
NET "cam_y_d[1]" LOC = R11;
NET "cam_y_d[2]" LOC = T11;
NET "cam_y_d[3]" LOC = T12;
NET "cam_y_d[4]" LOC = V12;
NET "cam_y_d[5]" LOC = N10;
NET "cam_y_d[6]" LOC = P11;
NET "cam_y_d[7]" LOC = M10;
# DDR Pin assign
NET "f_ddr_d[0]" LOC = M16;
NET "f_ddr_d[1]" LOC = M18;
NET "f_ddr_d[2]" LOC = L17;
NET "f_ddr_d[3]" LOC = L18;
NET "f_ddr_d[4]" LOC = H17;
NET "f_ddr_d[5]" LOC = H18;
NET "f_ddr_d[6]" LOC = J16;
NET "f_ddr_d[7]" LOC = J18;
NET "f_ddr_d[8]" LOC = N17;
NET "f_ddr_d[9]" LOC = N18;
NET "f_ddr_d[10]" LOC = P17;
NET "f_ddr_d[11]" LOC = P18;
NET "f_ddr_d[12]" LOC = T17;
NET "f_ddr_d[13]" LOC = T18;
NET "f_ddr_d[14]" LOC = U17;
NET "f_ddr_d[15]" LOC = U18;
NET "f_ddr_a[0]" LOC = H15;
NET "f_ddr_a[1]" LOC = H16;
NET "f_ddr_a[2]" LOC = F18;
NET "f_ddr_a[3]" LOC = J13;
NET "f_ddr_a[4]" LOC = E18;
NET "f_ddr_a[5]" LOC = L12;
NET "f_ddr_a[6]" LOC = L13;
NET "f_ddr_a[7]" LOC = F17;
NET "f_ddr_a[8]" LOC = H12;
NET "f_ddr_a[9]" LOC = G13;
NET "f_ddr_a[10]" LOC = E16;
NET "f_ddr_a[11]" LOC = G14;
NET "f_ddr_a[12]" LOC = D18;
NET "f_ddr_cke" LOC = D17;
NET "f_ddr_we" LOC = K12;
NET "f_ddr_ba[0]" LOC = H13;
NET "f_ddr_ba[1]" LOC = H14;
NET "f_ddr_clk" LOC = G16;
NET "f_ddr_nclk" LOC = G18;
NET "f_ddr_ras" LOC = K15;
NET "f_ddr_cas" LOC = K16;
NET "f_ddr_odt" LOC = K14;
NET "f_ddr_udqs" LOC = N15;
NET "f_ddr_udqsn" LOC = N16;
NET "f_ddr_ldqs" LOC = K17;
NET "f_ddr_ldqsn" LOC = K18;
NET "f_ddr_udqm" LOC = L15;
NET "f_ddr_ldqm" LOC = L16;
# LCD Pin assign
NET "lcd_r[0]" LOC = C14;
NET "lcd_r[1]" LOC = D14;
NET "lcd_r[2]" LOC = A15;
NET "lcd_r[3]" LOC = C15;
NET "lcd_r[4]" LOC = E13;
NET "lcd_r[5]" LOC = F13;
NET "lcd_r[6]" LOC = A14;
NET "lcd_r[7]" LOC = B14;
NET "lcd_g[0]" LOC = A13;
NET "lcd_g[1]" LOC = C13;
NET "lcd_g[2]" LOC = A12;
NET "lcd_g[3]" LOC = B12;
NET "lcd_g[4]" LOC = A11;
NET "lcd_g[5]" LOC = B11;
NET "lcd_g[6]" LOC = F9;
NET "lcd_g[7]" LOC = G9;
NET "lcd_b[0]" LOC = D9;
NET "lcd_b[1]" LOC = A8;
NET "lcd_b[2]" LOC = B8;
NET "lcd_b[3]" LOC = C8;
NET "lcd_b[4]" LOC = D8;
NET "lcd_b[5]" LOC = A6;
NET "lcd_b[6]" LOC = B6;
NET "lcd_b[7]" LOC = A7;
NET "lcd_spclk" LOC = A4;
NET "lcd_de" LOC = C5;
NET "lcd_hsync" LOC = A5;
NET "lcd_vsync" LOC = C7;
# ARM EBI Pin assign
NET "ebi_d[0]" LOC = N4;
NET "ebi_d[1]" LOC = P4;
NET "ebi_d[2]" LOC = P3;
NET "ebi_d[3]" LOC = L6;
NET "ebi_d[4]" LOC = M5;
NET "ebi_d[5]" LOC = U2;
NET "ebi_d[6]" LOC = U1;
NET "ebi_d[7]" LOC = T2;
NET "ebi_d[8]" LOC = T1;
NET "ebi_d[9]" LOC = P2;
NET "ebi_d[10]" LOC = P1;
NET "ebi_d[11]" LOC = N2;
NET "ebi_d[12]" LOC = N1;
NET "ebi_d[13]" LOC = M3;
NET "ebi_d[14]" LOC = M1;
NET "ebi_d[15]" LOC = L2;
NET "ebi_ncs" LOC = E1;
NET "ebi_nrd" LOC = F4;
NET "ebi_nwe" LOC = F3;
NET "ebi_a[0]" LOC = L1;
NET "ebi_a[1]" LOC = K2;
NET "ebi_a[2]" LOC = K1;
NET "ebi_a[3]" LOC = L4;
NET "ebi_a[4]" LOC = L3;
NET "ebi_a[5]" LOC = J3;
NET "ebi_a[6]" LOC = J1;
NET "ebi_a[7]" LOC = H2;
NET "ebi_a[8]" LOC = H1;
NET "ebi_a[9]" LOC = K4;
NET "ebi_a[10]" LOC = K3;
NET "ebi_a[11]" LOC = L5;
NET "ebi_a[12]" LOC = K5;
NET "ebi_a[13]" LOC = H4;
NET "ebi_a[14]" LOC = H3;
NET "ebi_a[15]" LOC = L7;
NET "ebi_a[16]" LOC = K6;
NET "ebi_a[17]" LOC = G3;
NET "ebi_a[18]" LOC = G1;
NET "ebi_a[19]" LOC = J7;
NET "ebi_a[20]" LOC = J6;
NET "ebi_a[21]" LOC = F2;
NET "ebi_a[22]" LOC = F1;
NET "ebi_a[23]" LOC = H6;
NET "ebi_a[24]" LOC = H5;
NET "ebi_a[25]" LOC = E3;
# PlanAhead Generated IO constraints
NET "cam_x_d[*]" IOSTANDARD = LVTTL;
NET "cam_y_d[*]" IOSTANDARD = LVTTL;
NET "ebi_a[*]" IOSTANDARD = LVTTL;
NET "ebi_d[*]" IOSTANDARD = LVTTL;
NET "f_ddr_cke" IOSTANDARD = SSTL18_II;
NET "f_ddr_cas" IOSTANDARD = SSTL18_II;
NET "f_ddr_clk" IOSTANDARD = DIFF_SSTL18_II;
NET "f_ddr_nclk" IOSTANDARD = DIFF_SSTL18_II;
NET "f_ddr_ldqm" IOSTANDARD = SSTL18_II;
NET "f_ddr_ldqs" IOSTANDARD = DIFF_SSTL18_II;
NET "f_ddr_ras" IOSTANDARD = SSTL18_II;
NET "f_ddr_odt" IOSTANDARD = SSTL18_II;
NET "f_ddr_udqm" IOSTANDARD = SSTL18_II;
NET "f_ddr_udqs" IOSTANDARD = DIFF_SSTL18_II;
NET "f_ddr_we" IOSTANDARD = SSTL18_II;
NET "f_ddr_vref" IOSTANDARD = SSTL18_II;
NET "f_ddr_a[*]" IOSTANDARD = SSTL18_II;
NET "f_ddr_ba[1]" IOSTANDARD = SSTL18_II;
NET "f_ddr_ba[0]" IOSTANDARD = SSTL18_II;
NET "f_ddr_d[*]" IOSTANDARD = SSTL18_II;
NET "lcd_r[*]" IOSTANDARD = LVTTL;
NET "lcd_g[*]" IOSTANDARD = LVTTL;
NET "lcd_b[*]" IOSTANDARD = LVTTL;
NET "cam_x_href" IOSTANDARD = LVTTL;
NET "cam_x_mclk" IOSTANDARD = LVTTL;
NET "lcd_vsync" IOSTANDARD = LVTTL;
NET "lcd_spclk" IOSTANDARD = LVTTL;
NET "lcd_hsync" IOSTANDARD = LVTTL;
NET "lcd_de" IOSTANDARD = LVTTL;
NET "ebi_nwe" IOSTANDARD = LVTTL;
NET "ebi_ncs" IOSTANDARD = LVTTL;
NET "clk" IOSTANDARD = LVTTL;
NET "ebi_nrd" IOSTANDARD = LVTTL;
NET "cam_y_vsync" IOSTANDARD = LVTTL;
NET "cam_y_pclk" IOSTANDARD = LVTTL;
NET "cam_y_mclk" IOSTANDARD = LVTTL;
NET "cam_y_hsync" IOSTANDARD = LVTTL;
NET "cam_y_href" IOSTANDARD = LVTTL;
NET "cam_x_vsync" IOSTANDARD = LVTTL;
NET "cam_x_pclk" IOSTANDARD = LVTTL;
NET "cam_x_hsync" IOSTANDARD = LVTTL;

里面带有f_前缀的是DDR的信号，约束有什么问题吗，求解答。

zongkai2003

回复 1# zongkai2003


    已解决，是DDR有几个特殊的pin没约束到，mcb1_rzq和mcb1_zio

csqorpheus

我也有同样的问题，如何给mcb1_rzq  mcb1_zio 约束？