折叠式共源共栅的极点问题

feynmancgz

回复 20# jxjxhwx


    because it is a feedback loop. Try to use current way to analize this circuit

haozhou812

个人觉得M5漏端的寄生极点还是存在的。M5源端的对地寄生电容会分掉从左边上面下来的小信号电流，使得流过M5的小信号电流减小，进而镜像到M6的信号给衰减了。
至于提到的电容倍增效应，尽管M5的栅端和漏端上的信号是反向的，但不会产生类似密勒效应的效果，M5的漏端小信号电压并不会放大多少，设若M9和M5的跨导相等，M9的源端和M5的栅端小信号电压变化应该差不多，因为两个管子流过相同的小信号电流（暂不考虑寄生电容）。
刚刚手算了下左边端点的对地阻抗（即M5的栅端），确实存在两个极点和一个左半平面零点，没法画图标注，不好给出公式，零点和极点的数量级相当，都是管子的跨导除以寄生电容，具体可以推算下，这样应该还会存在一个极点，也印证原来的想法，由M5漏端寄生电容所引起的信号衰减。有兴趣可以画下小信号图分析下，希望我没算错。
至于负反馈而引起M5漏端阻抗很小，这个需要考虑下。如果M9的栅端是输入端，上面带的是电流源，这样的buffer结构确实有减小阻抗的意思。但folded-cascode的结构，信号是从上面的电流源下来。手算出来并没有看到这个极点在很高频。
希望能对大家有所帮助。睡觉前推算小信号图，有可能会错，希望有人验证下。

haozhou812

个人觉得M5漏端的寄生极点还是存在的。M5源端的对地寄生电容会分掉从左边上面下来的小信号电流，使得流过M5的小信号电流减小，进而镜像到M6的信号给衰减了。
至于提到的电容倍增效应，尽管M5的栅端和漏端上的信号是反向的，但不会产生类似密勒效应的效果，M5的漏端小信号电压并不会放大多少，设若M9和M5的跨导相等，M9的源端和M5的栅端小信号电压变化应该差不多，因为两个管子流过相同的小信号电流（暂不考虑寄生电容）。
刚刚手算了下左边端点的对地阻抗（即M5的栅端），确实存在两个极点和一个左半平面零点，没法画图标注，不好给出公式，零点和极点的数量级相当，都是管子的跨导除以寄生电容，具体可以推算下，这样应该还会存在一个极点，也印证原来的想法，由M5漏端寄生电容所引起的信号衰减。有兴趣可以画下小信号图分析下，希望我没算错。
至于负反馈而引起M5漏端阻抗很小，这个需要考虑下。如果M9的栅端是输入端，上面带的是电流源，这样的buffer结构确实有减小阻抗的意思。但folded-cascode的结构，信号是从上面的电流源下来。手算出来并没有看到这个极点在很高频。
希望能对大家有所帮助。睡觉前推算小信号图，有可能会错，希望有人验证下。

feynmancgz

回复 25# jxjxhwx


    Sorry. I made a mistake.
    I will explain it much more clearly. I don't calculate it accurately, just explain it intuitively.
    Firstly, let us discuss the resistance at drain of M5 at low frequency. If the voltage at drain of M5 increase, the voltage at drain of M9 wil be very high because of high gain which means the voltage at gate of M5 will be high, if take Cgd into account, there will have current flowing from gate of M5 to its drain. it seems that it will show negative resistance. But do not forget the feedback path. High voltage at the gate of M5 also means M5 will drive much more current from the drain of M5. So it's negative or positive ? Seems hard to say. My argument is M5 is an amplifier, but Cgd of M5 cannot amplify signal. So M5 itself will drain much more current than Cgd it self. So We could say the resistance at drain of M5 is very low at low frequency. If calculate it and does not take Cgd into consideration, I think it will show low resistance.
     Actually, taking Cgd into account for your circuit analysis will make the problems very complex. So I highly recommend not to take it into account except when you do nanometer circuit design. Just beware of the effect of Cgd when you design your circuit. For hand calculation, it will make the problem very complex.
    Then goes to high frequency, That's where I made a huge mistake. The pole at the drain of M5 will not be that high as the loop gain will be low at high frequency. But it still higher than the pole of the drain of M9. The pole of the drain of M5 really exist. You said that the signal will not flow through M5. You are right if you were talking about output signal. But this saying is misleading. Consider there is a signal flow to the drain of M9. You said the signal will not flow through M5. But the real signal we are talking about is the signal flow to the drain of M9. This signal actually will split into two signal. One signal flow to the gate of M5, then this signal will introduce output signal. But there is another signal that flow through M5 and M9 themselves. How large is this signal will influence another signal that flow to the gate of M5. So the pole at the drain of M5 will influence the behavior of the circuit.

lovexxnu

回复 1# jxjxhwx


   电路上的所有零极点都会影响输出，不存在不在信号通路上的点不影响输出这一说

fuyibin

   

晶体管M5的漏端的RC时间常数在gm/C数量级，但是感觉M5漏端不在信号通路上，所以这个极点不会出现在运放 ...
jxjxhwx 发表于 2013-3-21 16:05

                               
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这个帖子扯淡扯的好长啊，实在看不下去了
这个问题其实意义并不大，而且答案很简单
M5 drain肯定有影响，只是被casode M9/M10 relieve了
要想有明确数学关系，自己推公式
其实有个简单的方法，在M5 drain挂 1KF cap，simulation里肯定可以看到
空谈误国啊！......