Cadence SH is looking for Principal/Lead Physical Design Engineer

kengteng

Cadence SH is looking for Principal/Lead Physical DesignEngineer

If you have interest, PLS send yourCV to zhangyl@cadence.com

SOC-RPhysical Design Team

Position: Principal/Lead Physical Design Engineer

Location: Shanghai

Position Description:

-Perform physical designimplementation, including synthesis, floor planning, power grid design, placeand route, clock tree synthesis, timing closure, power/signal integritysignoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure,and physical design project management.

-The candidate will have theopportunity to work on many varieties of challenging designs, i.e. low powerand high speed design. The responsibility includes participating in or leadingnext generation physical design, methodology and flow development.

                                                         

Position Requirements:         

1.BS degree with 10+ years ofapplicable experience, MS degree with 7+ years of applicable experience inelectrical engineering, microelectronics.

2.Experienced with ASIC design flow,hierarchical physical design strategies, methodologies and understand deepsub-micron technology issues.

3.Solid knowledge on LP Design, DFT,static timing analysis, EM/IR-Drop/crosstalk analysis, formal verification,physical verification, DFM.

4.Successful track records of tapingout complex, 65/40/28 nm SOC chips.

5.Automation and programming-minded,solid coding experience in Makefile/Tcl/Tk/Perl.

6. Self-motivated, able to workindependently or as a team player, excellent verbal and written communicationskills in English.