求教各位icc中create mw lib的问题[已解决]

Simon0827

小弟在create mw lib后，import design时第一个module就显示undefined，请问大神能帮助指导下么？
所用库http://bbs.eetop.cn/viewthread.php?tid=301894&highlight=milkyway%2Blef(感谢前辈分享)

1.create mw lib
tcl:create_mw_lib -technology /data/stu13/Simon/smic180/digital/sc/apollo/tf/smic18_6lm.tf -mw_reference_lib {/data/stu13/Simon/smic180/digital/sc/apollo/smic18} -open /data/stu13/Simon/0124/i_clkctrl
report:Start to load technology file /data/stu13/Simon/smic180/digital/sc/apollo/tf/smic18_6lm.tf.
Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 480) (TFCHK-014)
...
Warning: Layer 'METAL6' has a pitch 0.95 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Technology file /data/stu13/Simon/smic180/digital/sc/apollo/tf/smic18_6lm.tf has been loaded successfully.

2.import design
tcl:set search_path /data/stu13/Simon/smic180/digital/sc/synopsys
set link_library "typical.db fast.db slow.db"
set target_library {typical.db fast.db slow.db}
import_designs -format verilog -top i_clkctrl -cel i_clkctrl -rp_constraint /data/stu13/Simon/0124/sdc.tcl {/data/stu13/Simon/0124/i_clkctrl.v}

report:*****    Start Pass 1 *****
Begin loading DB for bus info.
End of loading DB for bus info.Elapsed =    0:00:03, cpu =    0:00:03
*****  Pass 1 Complete *****
Elapsed =    0:00:00, CPU =    0:00:00
*****  Verilog hdl translation! *****
*****    Start Pass 2 *****
Error: Module 'DFFX1' is not defined.  (MWNL-297)
hdlCleanupDBLibrary:
Error: Verilog parser cannot parse the /data/stu13/Simon/0124/i_clkctrl.v source file. (MWNL-047)

论坛上之前发过类似问题的帖子，但是好像没有完成的跟进解决http://bbs.eetop.cn/viewthread.php?tid=340798&highlight=mw%2Blib

求助于各位大神，不胜感激

xjg@hmes

回复 1# Simon0827


    确认以下内容：
1、lib/db中有无此cell的定义；
2、MilkyWay Data FRAM中有无此cell生成。
3、Netlist中关于此cell的定义是否正确

Simon0827

回复 2# xjg@hmes


    感谢帮助，我刚才做了检查

    1.对应db的lib中存在DFFX1 cell
    2.Milky Way的Data FRAM是下载到的库内smic180/digital/sc/apollo/smic18/FRAM自有的,抱歉我刚接触这些还不懂自己生成
          其中FRAM内的对应cell文件名叫做DFFX1_1，在CEL中对应cell文件名叫做DFFX1_2
    3.nl中的定义是正确的

        另外请问，我在create nw lib后，得到的自己的project为/data/stu13/Simon/0124/i_clkctrl
        做完create后，内部只有3个文件lib,lib_1,lib_bck.请问这个是正常的吗？
        在import design报错后，内部多了一个CEL的folder，里面有两个文件DFFX1:1,DFFX1:1.lock

        请问是否是creat mw lib出了问题？Reference Lib阅读时有几个warning
Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitNomResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitMaxResistance'. (line 480) (TFCHK-014)
Warning: Cut layer 'VIA12' has a non-cross primary default ContactCode 'via1'. (line 498) (TFCHK-092)
Warning: Cut layer 'VIA23' has a non-cross primary default ContactCode 'via2'. (line 516) (TFCHK-092)
Warning: Cut layer 'VIA34' has a non-cross primary default ContactCode 'via3'. (line 534) (TFCHK-092)
Warning: Cut layer 'VIA45' has a non-cross primary default ContactCode 'via4'. (line 552) (TFCHK-092)
Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.535 or 0.485. (TFCHK-049)
Warning: Layer 'METAL2' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL3' has a pitch 0.56 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Warning: Layer 'METAL5' has a pitch 0.61 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL6' has a pitch 0.95 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
        但是最后也有生成成功的提示
Technology file /data/stu13/Simon/smic180/digital/sc/apollo/tf/smic18_6lm.tf has been loaded successfully.
        求教这些warning的出现是否影响了create lib的结果？
        谢谢高人

xjg@hmes

回复 3# Simon0827


    这种wangning没问题，不影响后面的读入
再继续检查以下内容：
1、环境设置是否正确，如link_libary、target library等
2、实行check_library、check_design命令查看结果中的warning/error

这种错误我只能凭经验告诉你怎么去找解决方法，具体分析还得靠你自己细腻的check。

icfbicfb

这啥版本icc啊，还import_design ，

用read_verilog

ref lib要对，否则总是link error

Simon0827

回复 4# xjg@hmes


    感谢您的帮助！抱歉我昨天临时有事出去，现在按您说的继续检查

Simon0827

回复 5# icfbicfb




    2009.06 ICC SP1，请问您说的link error是我的lib没有去做link的工作还是说在link时会有error报出？

Simon0827

回复 4# xjg@hmes


    能向您再请教下吗？我set了一个.synopsys_icc.tcl,也做了一些别的检查。
在指令import_designs -format verilog -top i_clkctrl -cel i_clkctrl -rp_constraint /data/stu13/Simon/0127/sdc.tcl {/data/stu13/Simon/0127/i_clkctrl.v}之后，得到了下面的log

Loading db file '/data/stu13/Simon/smic180/digital/sc/synopsys/typical.db'
Loading db file '/cad/synopsys/icc_2009.06-SP1/libraries/syn/gtech.db'
Loading db file '/cad/synopsys/icc_2009.06-SP1/libraries/syn/standard.sldb'

Warning: /data/stu13/Simon/0127/for_synPR/smic18: bus naming style _<%d> is not consistent with main lib. (MWNL-111)
请问这个Warning是否会影响lib的链接？(属于比较重的warning?)所以才会造成之前问题的undefined module？
Spec里面说
If you do not specifythe bus naming style, %d is used.
请问是否有别的常用bus naming style设置？

Simon0827

请恕小弟愚陋，花了不少功夫才解决这个简单问题。
最后将FRAM内的文件手动更名库即可以正常链接。
例如DFFX_1改为DFFX:1,不会贴图见谅

jk_red

回复 9# Simon0827


   这是因为版本问题吗  你有没有试一下2010的版本可能不用改名就可以了