Cadence SH 招聘 Principal Product Engineer-----DDR IP

kengteng

Principal ProductEngineer-----DDR IP

[url=]If you haveinterest, PLS send your update CV to zhangyl@cadence.com[/url]

PositionDescription:

Cadence is looking for an individual to work in designIP team. The group provides configurable DDR memory controller and PHY IP forASICs. The job will be mainly focused on providing post technical support tocustomers; however there will be a variety of other engineering tasks that willallow the candidate to expand skills and responsibilities.

Provide technical support to customersfor integration of IP into ASICs including:

- Debugging of customers’ simulation or siliconissues.

- Reviewing of customers’ design integration of ourIPs.

- Reviewing static timing reports to assist withcustomers’ timing closure.

- Answering technical questions about IP operation.

- Train field engineers in IP operation.

- Interface with the R&D Team to bridge productimprovements and resolve customer issues.

PositionRequirements:         

- Excellent oral and written communication

- Good Englishcommunication skill

- BS  8+ years of prior work-experience or MS6+ years of prior work-experience

- All front-end skills – RTL design &verification in Verilog, synthesis, static-timing analysis, DFT

- Back-end skills – place & route, physicalverification, timing closure

- Time management skills sufficient to balancemultiple high-priority projects.

- Willingness to learn new skills and perform tasksthat often go outside area of current expertise.

AdditionalDesirable Qualifications:

- Experience with Static Timing scripts and reportanalysis

- Familiarity with DDR memory operation, systemapplications, AXI, OCP, AHB

- Familiarity with Frame maker

- Scripting – in Perl, TCL, etc..