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到年底了,板上有想要跳槽的吗? 内部直推,简历请发到邮箱 knight.shi@gmail.com
公司中文名 晶晨半导体 ,正在招聘模拟版图设计工程师,有过power/RF/High speed layout 经验的都受欢迎。最好有两年以上工作经验。
JD 如下:
职位描述:
Responsibilities:
Responsible for all aspects of custom IC layout design and implementation of mix signal CMOS ASICs, including participating in the layout of analog/mixed signal circuit, DRC/LVS/LPE verification, block/chip floor plan, power/clock distribution and chip assembly.
Qualifications:
1. Custom IC layout design training certificate, BSEE preferred. 2. Familiar with Cadence layout design tools is required. 3. Familiar with DRC/LVS/LPE tools is required. 4. Familiar with CMOS analog IC schematics is required. 5. Good organizational and problem solving skills. 6. Good communication skill in English and Chinese.
工作职责:
1. 负责定制芯片的版图设计与混合信号CMOS定制芯片的实现;
2.负责模拟/混合信号电路的版图分类,DRC/LVS/LPE验证,模块/芯片的布局,电源/时钟的分布以及芯片集成。
任职资格:
1. 取得定制芯片版图设计培训证书BSEE者优先;
2. 熟悉版图设计工具Cadence;
3. 熟悉 DRC/LVS/LPE 验证工具;
4. 熟悉CMOS模拟芯片图表;
5. 较好的组织能力和问题解决能力;
6. 较好中英文沟通表达能力。 |
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