verdi scripts for design analysis

anovickis

Included are:
- Script to create list of design files which are used by Verdi
     list_verdi_source_files.tar.gz
- This script will show the path of `include file using npi commands.
     npi_inc_file.tgz
- Dump the design hierarchy tree in plain text format, which canbe post-processed
    dmp_hier_tree.tar.gz
    dmp_hier_tree_C.tar.gz
- Dump the design hierarchy tree in CSV (Comma Separated Values) format
   dmp_hier_csv.tar.gz
   dmp_hier_csv_C.tar.gz
- Module/Instance information
Dump the module name of instances
extract_file_info.tar.gz
extract_file_info_C.tar.gz
Print all the module names of the design in plain text format
list_all_modules.tar.gz
list_all_modules_C.tar.gz
Dump the file name and line number for each module in the design withtext format file
dmp_hier_file.tar.gz
dmp_hier_file_C.tar.gz
Dump port and parameter information for each module instance/primitive
npi_for_mixed.tar.gz
npi_for_mixed_C.tar.gz
Find the source file and its line number from the specified instance name
find_source.tar.gz
find_source_C.tar.gz
Find the instance and gate name from the specified regexp
find_instance_name.tar.gz
find_instance_name_C.tar.gz

Trace Driver/Load/Connectivity

npi_sig_2_primitive_inst_conn.htm
npi_sig_2_primitive_inst_conn_dump.htm
get_connect.tar.gz
trace_drv_load_C.tar.gz

Print the information of the constant found from every assignment (includingcontinuous assign and assignment)

get_const_value.tar.gz
get_const_value_C.tar.gz

Report the verilog netlist overview like port count, hierarchical scope count,primitive cell count (not including UDP) for the given scope
get_netlist_overview.tar.gz
get_netlist_overview_C.tar.gz

Print the full name for all registers within the given design
list_all_register.tar.gz
list_all_register_C.tar.gz

Print every net/var (defined as wire, reg and logic) name in dump_all_net.log
dump_all_net.tar.gz
dump_all_net_C.tar.gz
Print all port high connections of the specified instance or all connectedinstances of the specified net.
dump_instance_net.tcl
dump_instance_net_C.tar.gz



Dump the target instance’s port connection status and detect the open pin ifthe port is floating.
dmp_port_conn.tar.gz
npi_sig_2_primitive_inst_conn.htm
npi_sig_2_primitive_inst_conn_dump.htm

Check the connectivity between 2 given signals. This Tcl script uses the NPI L1command and return the answer YES/NO after checking the connectivityrelationship between 2 signals.
npi_L1_check_conn_npi_example.tar.gz

Detect all snake paths for the given target net. This script is written usingthe OLD model, set the environment variable NOVAS_OLD_NPI before executing yourscript if your Verdi version is 2012.01 or later
verdi_api_netlist_api_snakepath.tar.gz


If a user has e systems that are checking the metastability, they need to checkthat both q and d pins are in the VHDL or Verilog path. If d and q are from amixed language then they have to find an equivalent net but in the otherlanguage
Check_Metastable.tar.gz

Design Manipulation

VIA Design Manipulation Appsinclude a set of C-APIs/Tcl to let users manipulate their designs and thecorresponding files (SDC/CPF/UPF).

• Chip Integration
• Instance Grouping/Ungrouping
• Drop inactive lines from the entire design     according to the macro definition. (Requires a version newer than     2012.01)
• Drop_inactive_line.tar.gz
• nECO does not support creating an empty     module with ports. This Perl script creates a module and invokes the nECO     command to create a port for it.
• Create_Module.tgz

FSDB investigation

• Use the $fsdbAutoswitchDumpfile dumping     command for regression. This script enables running both     multiple simulations in parallel (regression) and fsdbAutoSwitchDumpfile.     Since multiple simulations need to run in parallel, they cannot have the     same base FSDB name; therefore, a unique base file name is generated for     each test as all tests dump their files to a single common “dumpdir”     directory. Because the base name is different for each test, no naming     conflicts exist, so the FSDB files, the log files, and the Virtual File     (.vf) files are all there and complete when the regression is done.
  • run_nc_autosdf.pl.tgz
• This Tcl/TK script will automatically     populate a Watch Window with all signals in the current scope and will     update when the scope changes.
  • Auto_Watchsignals.tar.gz
• This Tcl/TK script adds a command called ‘Duty Cycle’     to the bottom of the Waveform menu in nWave. After selecting a set of     one-bit signals in nWave, placing the cursor and the marker, and then     selecting ‘Duty Cycle’, a window will open.
  • duty_cycle_v2.tgz
• This set of Tcl scripts takes a normal digital bus     and then creates a new Fixed Point Fractional Representation bus. The     user can specify signed or unsigned and the size of the integer part     (IWL).
  • Bus2FPFN.tgz
• This script creates an alias table in nWave Signal File     format from alias extraction output.
• AppliAlias.tar.gz
• This script dumps the total time of each value between     the cursor time and marker time.
• ReportDistribution.tar.gz
• This script dumps all signal names and the times     where the pulse is smaller than the specified time.
• ReportSmallPulse.tar.gz
• This Tcl script provides the statistics     of signal value in specific time period.
  • 20111117_nWave_report_toggle_in_range.tar.gz

Debug Automatiion

• Automatically trace all Xs in the FSDB file and     print out a text report in batch mode. This script includes 3     parts:
  • Step 1. List all Xs from the specified      FSDB file.
  • Step 2. Trace X for each signal from the result      of Step 1.
  • Step 3. Generate the report of tracing results of Step      2.

• tracex_10_reset_TCL.tgz
• tracex_10_reset_C.tgz
• This Tcl package will automatically allow the     user to load a portion of the design dependent upon the signal selected in     the nWave window.
  • tcl_createvtop_loaddesign.tar.gz
• This Tcl script allows the user to save any signals     selected in nWave to a VCD file. This includes, events, logical operations     etc. The default VCD file name is nWave_number.vcd, where number is     determined by the Tcl clock function, so no 2 files will have the     same name. See below to change the file name.
  • save_nWave_signals.tcl_v1.0.tgz
• Display all input port signal waveforms for the     selected npiModule cell on nWave Script.
• add_input_signal.tar.gz
• add_input_signal_C.tar.gz
• Tcl script to check the violation of simulator report     with the Verdi system.
• violation.tar.gz

Tool interoperating

Simulators

• This shell script converts Synopsys DVE signal     session *.tcl file to nWave’s signal *.rc file.
  • dve2rc_3.tgz
• This script translates the do file to nWave’s rc     file. The do file contains Cadence Signalscan Waves commands that can     be loaded and executed by Signalscan Waves. This translator only     extracts the information where the rc file has     a corresponding command and translates it to rc file’s syntax.
  • do2rc.tar.gz
• This is supposed to help user share information     with group using signalscan. It will convert all the signals/groups and     zero delay information. The compressed file has the source code and the     Linux/Solaris executables.
  • rc2do_a.tar.gz
• This Perl script will convert MTI .do file     to ”.rc” file for nWave/Verdi.
• mtido-rc.pl.tgz
• This script converts Cadence cds.lib to Novas     novas.rc automatically for library mapping. It supports the nested     structure. (Limitation: This utility only works for specifying “ABSOLUTE     PATH” , not “RELATIVE PATH” for conversion.)
• nc2novasrc.tar.gz
• This is a new Perl script called virsim2nWave that     converts Synopsys virsim *.cfg file to signal.rc for nWave/Verdi.
• virsim2nWave.zip
• The users of Cadence NCsim would be able to compile and     run Verdi with minimum set up. After pointing to this Perl script, the     user can just use the same script or the same Makefile that is used for     running the NC simulator.
  • Ncscript.tar.gz
• Print the target module information into a wrapper map     file.
• create_wrapper_lib.tar.gz
• create_wrapper_lib_C.tar.gz

Formal Tools

• Please check following link for the example to Display     CLP (Cadence/Encounter Conformal Low Power) report with Power Aware Verdi.     (Please import the design and CPF file first before running the Tcl     script)
  • CLP2Verdi.tar.gz

Annotate User-definded Data

• Verdi allows you to annotate your own data to the Verdi     system so that you can browse the data easily. For example, you can     annotate power consumption data from a third party tool and browse the     information conveniently in the familiar Verdi environment. Currently, the     feature is considered beta.
  • User_Defined_Annotation.pdf

virsim

拜托，打一个大一点的包吧，这么多要多少积分呀！

Newstyle

打个包吧，否则很难搞的，要积分的话，可以加上售价！

anovickis

By popular demand,

all scripts in one document

virsim

嗯，下载了

caoluniu

好东西，谢谢啦

Newstyle

多谢！！！！！！！！！

jaja65

多謝樓主

hsieh531

學習是為了走更長遠的路.
謝謝您.

薇儿安蓝

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