你如果自己写这个IP核的话，我们可以提供I2C的 Verification IP 给你。这样你可以来Verify你写的I2C代码。
我们的I2C Verification IP： provides an effective & efficient way to verify the components
interfacing with I2C interface of an IP or SoC.
This VIP is a light weight VIP with easy plug-and-play interface so that there is no hit on the design time and the simulation time.
This VIP is compatible with Mentor Questa, Cadence NC and Synopsys VCS , and can be used for verification of I2C IP in standalone or in SoC environment.
主要Features：
• Fully compliant with Revision 03 and 2.1 of the I2C Bus Specification
• Full I2C Master and Slave functionality
- Master Transmitter/Master Receiver
- Slave Transmitter/Slave Receiver
• START , repeat START and STOP for all possible transfers
• Supports all Speed Modes: Standard Speed Mode (upto 100 kb/s), Fast Speed Mode (upto 400 kb/s), Fast Speed Mode Plus (upto 1Mb/s) and High Speed Mode (upto 3.4 Mb/s)
• Supports 7-Bit and 10-Bit addressing format
• Allows testing of varied bus traffic for Read, Write, General Call
• Supports scoreboard feature for end to end data integrity check
• Notifies the Testbench of significant events such as transactions, warnings, and protocol errors
• Built in I2C Bus Monitor provides extensive protocol checking
• Supports Multi-Master and Multi-Slave system
• Supports Arbitration and Clock Synchronization
• Supports START Byte, Device ID, Bus Clear and Clock Stretching
• Supports various error injection and detection
• Provides verification scalability using functional coverage
• Provides logging facility for bus traffic in the ASCII format and in user configurable mode
• Supports Callback in Master and Slave
• Supports timing checks in the Monitor
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发表于 2012-12-17 20:40:07
