请问一下F28335ADC模块的采样时间窗

vipjph

在ADC模块reference guide中
ADC时钟由ADCCLKPS和CPS寄存器确定，但是后面有一个ACQ_PS寄存器是控制扩展采样保持器的脉冲？

请问这究竟是什么意思？采样时间窗究竟起什么作用？
In addition, the ADC can be
tailored to accommodate variations in source impedances by widening the sampling/acquisition period.
This is controlled by the ACQ_PS[3:0] bits in the ADCTRL1 register. These bits do not affect the
conversion portion of the S/H and conversion process, but do extend the length of time in which the
sampling portion takes by extending the start of the conversion pulse

vipjph

采样窗口的大小确定ADC模块中采样电容的充电时间。

vipjph

ADC的时钟周期由ADCCLKPS和CPS决定，而ACQ_PS寄存器决定采样窗口的时间是几个ADCCLK，采样窗的作用是对输入的模拟信号进行采样转换。

如外设时钟是150MHz，ADCCLKPS=(0011b)，CPS=(0b),ACQ_PS=（0111b），则计算后ADCCLK=25MHz，采样窗口为8个(1/ADCLK).