Verilog HDL相关问题

hua良 · 发表于 2012-9-1 10:41:14

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module AND2(A,B,Y);
input A;
input B;
output Y;

wire A;
wire B;
wire Y;
assign Y=A&B;
endmodule

Error (12007): Top-level design entity "AND2" is undefined
Error: Quartus II 32-bit Analysis & Synthesis was unsuccessful. 1 error, 3 warnings
Error: Peak virtual memory: 307 megabytes
Error: Processing ended: Sat Sep 01 10:30:18 2012
Error: Elapsed time: 00:00:01
Error: Total CPU time (on all processors): 00:00:01
Error (293001): Quartus II Full Compilation was unsuccessful. 3 errors, 3 warnings
这样一个程序怎么有这么多错误啊，怎么回事？是不是我的软件设置问题？希望大家帮我解释下，谢谢了！