CMOS layout KungFu

pythonlong

好东西很多,银子却很少

pmu

missing the second half of the book

huxinhuwei

不是看的很懂!~......

breezerlxd

东西还不错，就是不全，

semico_ljj

Book Description
This text treats the physical design of very large scale integrated circuits gradually and systematically. It examines the design problem and the design process with the aim of evaluating the efficiency of automatic design systems through algorithmic analysis. The layout problem is viewed as a collection of sub-problems which can be individually solved efficiently and then effectively combined. Initially, the text reviews VLSI technology and then examines layout rules and cell generation techniques.

semico_ljj

Hardcover: 416 pages Publisher: Mcgraw-Hill College (February 21, 1996) Language: English

semico_ljj

Preface
1. Introduction .................................................................. 1
2. MOS Transistors ........................................................... 2
3. Fabrication of MOS Transistor ..................................... 5
4. Layout a Single Transistor .......................................... 11
First Stroke The basic transistor layout ..................... 12
Second Stroke Compact the transistor layout ................ 13
Third Stroke Speed up the transistor ........................... 17
Fourth Stroke Clean up the substrate Disturbances ...... 20
Fifth Stroke Balancing area, speed and noise ............ 26
Sixth Stroke Relief the stress ...................................... 29
Seventh Stroke Protect the gate ...................................... 30
Eighth Stroke Improve yield ..........................................32

semico_ljj

5. Layout Several Transistors ......................................... 34
Eighth Stroke Improve yield...........................................35
Re-visit
Ninth Stroke Close proximity .......................................36
Tenth Stroke Interdigitated layout ............................... 36
Eleventh Stroke Dummy transistor ................................... 41
Twelfth Stroke Two-dimension interdigitated layout ..... 43
Thirteenth Stroke Guard ring for the matched transistors ... 45
Fourteenth Stroke Keep NMOS away from N-well ............ 45
Fifteenth Stroke Orientate the transistor ........................... 46
Sixteenth Stroke Match the interconnects ......................... 47
Seventeenth Stroke The unmatchable .................................... 50
6. Verifying the Transistor Layout ................................. 52
Eighteenth Stroke Physical verification beyond DRC and
LVS ........................................................ 61

5&6是缺的！可惜！

kingkee

yi ban ban

song_rf

好书就要支持