Testing made easy

no1no1

For VHDL users Aldec provides "Open Source VHDL Verification Methodology" that causes the users of VHDL not migrate to SystemVerilog for using OVM and UVM methodologies in verifying their designs.
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Testing Made Easy:
http://www11.edacafe.com/video/flv_data/video_4594.flv

lixqing

Thank you so much!