对标准单元库加深理解有帮助的论文

amodaman

In this work, a simplified method for performing characterization of a standard cell is
presented. The method presented here is based on Synopsys models of cell delay and power
dissipation, in particular the linear delay model. This model is chosen as it allows rapid
characterization with a modest number of simulations, while still achieving acceptable accuracy.
Additionally, a guideline for developing standard cell libraries for use with Synopsys synthesis
and simulation tools and Cadence Placement-and-Routing tools is presented. A cell layout
library, built in accordance with the presented guidelines, was laid out, and a test chip, namely a
dual 4-bit counter, was built using the library to demonstrate the suitability of the method

Contents
I. Introduction .............................................................................................................................. 1
II. Background ............................................................................................................................. 3
2. 1. About Standard Cell Libraries ......................................................................................... 3
2. 2. Typical Standard Cell Based Design Flow ..................................................................... 4
2. 3. Standard Cell Development Process Flow ...................................................................... 6
2. 4. Review of Previous Works .............................................................................................. 8
III. Development of Layout and Abstract Library .................................................................... 10
3. 1. Requirements on the Library ......................................................................................... 10
3. 2. Layout Technique .......................................................................................................... 11
3. 2. 1. What Silicon Ensemble Does ................................................................................ 11
3. 2. 2. Requirements on the Layout Style ........................................................................ 13
3. 2. 3. Example of Cell ..................................................................................................... 18
IV. Timing and Capacitance Characterization .......................................................................... 20
4. 1. Timing Model and Aim of Characterization ................................................................. 20
4. 1. 1. Basic CMOS Timing Model and Definition of Terms .......................................... 21
4. 1. 2. Linear Delay Model .............................................................................................. 25
4. 1. 3. Definition of Setup Time ....................................................................................... 28
4. 2. Proposed Timing and Capacitance Characterization Method ....................................... 30
4. 2. 1. Input Capacitance Measurement ........................................................................... 30
4. 2. 1. 1. Basic Approach ................................................................................................. 30
4. 2. 1. 2. Input Capacitance Measurement for Combinational Cells ............................... 31
4. 2. 1. 3. Input Capacitance Measurement for Sequential Cells ...................................... 33
4. 2. 2. Non-tristate Delay Characterization ...................................................................... 36
4. 2. 2. 1. Intrinsic Delay Measurement ........................................................................ 36
4. 2. 2. 2. Transition Delay and Output Resistance Measurement ................................ 38
4. 2. 2. 3. Slope Sensitivity Measurement ..................................................................... 41
4. 2. 2. 4. SPICE Example of Capacitance and Delay Characterization
Simulation ..................................................................................................................... 43
4. 2. 2. 4. 1. Example for 2-input NAND Gate ......................................................... 44
4. 2. 2. 4. 2. Example for Simple D Flip-flop ............................................................ 49
4. 2. 5. Setup Time Characterization Using Bisection ...................................................... 52
4. 2. 5. 1. Discussion ..................................................................................................... 52
4. 2. 5. 2. SPICE Example ............................................................................................. 54
4. 2. 6. Tristate Cell Timing and Input/Output Capacitance Characterization .................. 58
4. 2. 6. 1. Intrinsic Delays and Enable Delay Determination ........................................ 60
4. 2. 6. 2. Determination of ipop Output Resistance ..................................................... 61
4. 2. 6. 3. Input Capacitance Determination .................................................................. 62
4. 2. 6. 4. Output Capacitance Determination ............................................................... 62
4. 2. 6. 5. Measurement of Output Resistances for Enable Delays ............................... 64
4. 2. 6. 5. Mesurement of Disable Delays ..................................................................... 64
4. 2. 6. 6. SPICE Example ............................................................................................. 64
5. Power Characterization ......................................................................................................... 71
5. 1. Basics of Power Dissipation .......................................................................................... 71
5. 1. 1. Static Power ........................................................................................................... 72
5. 1. 2. Dynamic Power ..................................................................................................... 73
5. 2. Synopsys Model of Power Dissipation ......................................................................... 78
5. 3. Proposed Power Characterization Method .................................................................... 82
5. 3. 1. Static Power Measurement .................................................................................... 82
5. 3. 1. 1. Basic Method ................................................................................................. 82
5. 3. 1. 2. SPICE Example ............................................................................................. 83
5. 3. 2. Dynamic Power Measurement for Simple Combinational Cells .......................... 84
5. 3. 2. 1. Basic Method ................................................................................................. 84
5. 3. 2. 2. SPICE Example ............................................................................................. 85
5. 3. 3. Dynamic Power Measurement for Sequential Cells and
Combinational Cells with Internal Loads .......................................................................... 89
5. 3. 3. 1. Basic Method ................................................................................................. 89
5. 3. 3. 2. SPICE Example ............................................................................................. 93
5. 3. 4. Dynamic Power Measurement for Tristate Cells ................................................ 100
5. 3. 4. 1. Basic Method ............................................................................................... 100
5. 3. 4. 2. SPICE Example – Complete File ................................................................ 108
VI. Example Design – Twin 4-bit Counter ............................................................................. 113
VII. Summary .......................................................................................................................... 117
Bibliography ............................................................................................................................ 118
APPENDIX I Instructions for LEF File Generation Process .................................................. 119
Vita ......................................................................................................................................... 136

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