希望哪位大神帮助解决一下啊,给小弟说说原因,谢谢了!!
AMS仿真时,我在执行到elaborating那一步的时候,就出现错误了,不能simulating 不知道你有没有遇到过呢,帮助解决一下吗,谢谢了!
Elaborating testlib.testfixture:config -ncelab testlib.testfixture:config -snapshot testfixture: ams1343411773460 -cdslib
/home/zrg/cadence_example/atest/cds.lib -hdlvar /home/zrg/cadence_example/atest/hdl.var
testlib.cds_globals:testfixture_config -errormax 50 -discipline logic -timescale 1ns/1ns -noparamerr -use5x4vhdl -status -delay_mode None -novitalaccl -update -omicheckinglevel standard -access +r-w-c
ncelab: *internal* (sv_seghandler - trapno -1).
please contact cadence design systems about this problem and provide enough information to help us reproduce it.
ncelab: memory usage -13.7M program + 43.9M data = 57.6M total
ncelab: cpu usage -0.0s system + 0.0s user = 0.0s total(0.0s, 100.0% CPU) error encountered during NC elaboration for configuration testlib.testfixture:config 我用的是IC5141+IUS56 IUS56实在eetop上面找到。。。 我之前有仿过它教程里面给的一个例子,最后也是这种错误,后面simulating就仿不下去了。
在发一次啊,别沉了 哪位遇到过呢,帮忙一下
希望哪位大神帮助解决一下啊,给小弟说说原因,谢谢了!!
AMS仿真时,我在执行到elaborating那一步的时候,就出现错误了,不能simulating 不知道你有没有遇到过呢,帮助解决一下吗,谢谢了!
Elaborating testlib.testfixture:config -ncelab testlib.testfixture:config -snapshot testfixture: ams1343411773460 -cdslib
/home/zrg/cadence_example/atest/cds.lib -hdlvar /home/zrg/cadence_example/atest/hdl.var
testlib.cds_globals:testfixture_config -errormax 50 -discipline logic -timescale 1ns/1ns -noparamerr -use5x4vhdl -status -delay_mode None -novitalaccl -update -omicheckinglevel standard -access +r-w-c
ncelab: *internal* (sv_seghandler - trapno -1).
please contact cadence design systems about this problem and provide enough information to help us reproduce it.
ncelab: memory usage -13.7M program + 43.9M data = 57.6M total
ncelab: cpu usage -0.0s system + 0.0s user = 0.0s total(0.0s, 100.0% CPU)
error encountered during NC elaboration for configuration testlib.testfixture:config
我用的是IC5141+IUS56 IUS56实在eetop上面找到。。。
我之前有仿过它教程里面给的一个例子,最后也是这种错误,后面simulating就仿不下去了。