sdram 求大侠指点

tangate

之前原程序用8bit数据进fifo变成64bit，再经过sdram（64bit）出来，再经过fifo还原出来，数据能完全还原，现在我改用32bit进fifo，我要做哪些更改，才能把原数据还原，不丢失？一下是我改的程序（加了tangate的是我改的），望高手指教！
1、出fifo，到sdram
`timescale 1ns / 100ps
module ccd_fifo_ctrl(
        clk,
        resetn,
        //sdram control signal
        SDRAM_BUS_REQ,
        SDRAM_BUS_ACK,
        SDRAM_ADS_n,
        SDRAM_Addr_out,
        SDRAM_Data_out,
        //SDRAM_Data_valid,
        //SDRAM_Data_in,
        SDRAM_R_Wn,
        //Camera output signal
        ccd_clk,
        ccd_vs,
        ccd_hs,
        ccd_de,
        ccd_data,
        ccd_sel,
        field_sel,
        write_frame_cnt
        );
input      clk;
input      resetn;
//sdram control signal
output               [1:0]write_frame_cnt;
output      SDRAM_BUS_REQ;
input      SDRAM_BUS_ACK;
output      SDRAM_ADS_n;
output [21:0]  SDRAM_Addr_out;
output [63:0]  SDRAM_Data_out;
//input     SDRAM_Data_valid;
//input [31:0]  SDRAM_Data_in;
output      SDRAM_R_Wn;
//Camera signal
input      ccd_clk;
input      ccd_vs;
input      ccd_hs;
input      ccd_de;
input [31:0]   ccd_data;
input      ccd_sel;    //0-->sensor1, 1-->sensor2
input      field_sel;
//---------------state--------------------
//
parameter c_w_idle = 5'b00001;
parameter c_w_req  = 5'b00010;
parameter c_w_ads  = 5'b00100;
parameter c_w_data = 5'b01000;
parameter c_w_wait  = 5'b10000;
reg [4:0] c_state;
//fifo control signal
wire      fifo_empty;
wire [63:0]  fifo_rdata;

//-----------sdram ack input delay-----------
reg sdram_bus_ack_d1;
always @(posedge clk or negedge resetn)
begin
if(!resetn)
  sdram_bus_ack_d1 <= 1'b0;
else
  sdram_bus_ack_d1 <= SDRAM_BUS_ACK;
end
//-----------sdram req--------------
reg SDRAM_BUS_REQ;
always @(posedge clk or negedge  resetn)
begin
if(!resetn)
  SDRAM_BUS_REQ <= 1'b0;
else if((c_state == c_w_req))
  SDRAM_BUS_REQ <= 1'b1;
else
  SDRAM_BUS_REQ <= 1'b0;
end
//------------sdram address---------------
//
reg [2:0] ccd_hs_syn;
reg [2:0] ccd_vs_syn;
reg ccd_hs_rising;
reg ccd_vs_rising;
always @(posedge clk or negedge resetn)
begin
if(!resetn)
begin
  ccd_hs_syn <= 3'b000;
  ccd_vs_syn <= 3'b000;
end
else
begin
  ccd_hs_syn <= {ccd_hs_syn[1:0], ccd_hs};
  ccd_vs_syn <= {ccd_vs_syn[1:0], ccd_vs};
end
end
always @(posedge clk or negedge resetn)
begin
if(!resetn)
  ccd_hs_rising <= 1'b0;
else if(!ccd_hs_syn[2] && ccd_hs_syn[1])
  ccd_hs_rising <= 1'b1;
else
  ccd_hs_rising <= 1'b0;
end
always @(posedge clk or negedge resetn)
begin
if(!resetn)
  ccd_vs_rising <= 1'b0;
else if(!ccd_vs_syn[2] && ccd_vs_syn[1])
  ccd_vs_rising <= 1'b1;
else
  ccd_vs_rising <= 1'b0;
end
/////////////////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////////////////////////////

reg [21:0] write_low,write_high,SDRAM_Addr_out;
always @ (posedge clk or negedge resetn)
if(!resetn)
  SDRAM_Addr_out <= 0;
else
  SDRAM_Addr_out <= {sensor_high_addr , write_low[19:0]};
always @ (posedge clk or negedge resetn)
if(!resetn)
  write_low <= 0;
else if (ccd_vs_rising)
  write_low <= 0;
else if(sdram_bus_ack_d1 && (SDRAM_BUS_ACK == 1'b0))
  write_low <= write_low + 4'd8;
reg [1:0] sensor_high_addr;
always @(posedge clk)
begin
   if(!resetn)
      sensor_high_addr <= 2'b10;
   else if(ccd_vs_syn[1:0] == 2'b01)
      sensor_high_addr <= sensor_high_addr + 1'b1;
end
assign write_frame_cnt = sensor_high_addr;
/////////////////////////////////////////////////////////////////////////////////////////////////////
//-----------SDRAM_R_Wn----------------
//
assign SDRAM_R_Wn = 1'b0;
//-----------SDRAM_Data_out-------------
//
assign SDRAM_Data_out = fifo_rdata;
//-----------SDRAM ADS-----------------
//
reg SDRAM_ADS_n;
always @(posedge clk or negedge resetn)
begin
if(!resetn)
  SDRAM_ADS_n <= 1'b1;
else if(c_state == c_w_ads)
  SDRAM_ADS_n <= 1'b0;
else
  SDRAM_ADS_n <= 1'b1;
end
//------------write data counter-------------
//
reg [7:0] wcnt;
always @(posedge clk or negedge resetn)
begin
if(!resetn)
  wcnt <= 8'h0;
else
begin
  if(c_state == c_w_data)
   wcnt <= wcnt + 1'b1;
  else
   wcnt <= 8'h0;
end
end
//------------state machine------------
//
always @(posedge clk or negedge resetn)
begin
if(!resetn)
  c_state <= c_w_idle;
else
begin
  case(c_state)
  c_w_idle:
   if(fifo_empty == 1'b0)
    c_state <= c_w_req;
  c_w_req:
   if(SDRAM_BUS_ACK)
    c_state <= c_w_ads;
  c_w_ads:
   c_state <= c_w_data;
  c_w_data:
   if(wcnt == 8'h7)
    c_state <= c_w_wait;
  c_w_wait:
   if(SDRAM_BUS_ACK == 1'b0)
    c_state <= c_w_idle;
  default:
   c_state <= c_w_idle;
  endcase
end
end
//-------------fifo rd-------------------
//
reg fifo_rd;
always @(c_state)
begin
if(c_state == c_w_data)
  fifo_rd <= 1'b1;
else
  fifo_rd <= 1'b0;
end

//---------------ccd write data---------------------
//
reg [15:0] ccd_clr_dly;
always @(posedge ccd_clk)
begin
   ccd_clr_dly <= {ccd_clr_dly[14:0] , ccd_hs};
end
reg [2:0] ccd_de_cnt;
always @(posedge ccd_clk or negedge resetn)
if(!resetn)
  ccd_de_cnt <= 3'b000;
else if (ccd_vs_rising)
  ccd_de_cnt <= 3'b000;
    else if(ccd_clr_dly[15:14] == 2'b10)
  ccd_de_cnt <= 3'b000;
else if (ccd_de_cnt == 3'b001 && ccd_de)//tangate 加上的，原先没有
     ccd_de_cnt <= 3'b000;//tangate 加上的，原先没有
else if(ccd_de)
  ccd_de_cnt <= ccd_de_cnt + 1'b1;
//////////////////////////////////////////
reg fifo_wr;
always @(posedge ccd_clk or negedge resetn)
if(!resetn)
  fifo_wr <= 1'b0;
else if (ccd_de_cnt == 3'b1 && ccd_de)//tangate 原先为7
  fifo_wr <= 1'b1;
else
  fifo_wr <= 1'b0;
reg [63:0] fifo_wdata;
always @(posedge ccd_clk or negedge resetn)
if(!resetn)
  fifo_wdata <= 64'h0;
else if(ccd_de)
  fifo_wdata <= {ccd_data, fifo_wdata[63:32]};//tangate 原先为【63:8】
wire fifo_empty_flag;
ccd_fifo_dc u1(
      .Reset(~resetn | ccd_vs_rising),
      .RPReset(1'b0),
      .WrClock(ccd_clk),
      .WrEn(fifo_wr),
      .Data(fifo_wdata),
      .RdClock(clk),
      .RdEn(fifo_rd),
        .Q(fifo_rdata),
        .Empty(),
        .Full(),
        .AlmostEmpty(fifo_empty_flag)
        );
reg [1:0] fifo_empty_syn;
always @(posedge clk or negedge resetn)
begin
if(!resetn)
  fifo_empty_syn <= 2'b11;
else
  fifo_empty_syn <= {fifo_empty_syn[0], fifo_empty_flag};
end
assign fifo_empty = fifo_empty_syn[1];
endmodule


2、出sdram，到fifo

module Sdram_Bayer2RGB(
input  clk_write,
input  resetn,
input        Hdmi_De,
input    Hdmi_hde,
input   Hdmi_vde,
output reg FIFO_Full,
input  FIFO_WR,
input [63:0] FIFO_WData,
input  clk_read,
output reg[31:0] data_out,
input  wire Hdmi_Vsync
);

wire [23:0] Hdmi_Pixdata;
wire read_de;

wire [63:0]  Fifo2_q;
wire [6:0] Fifo2_wrusedw;
reg    Fifo2_rdreq;

ff32 ff32(
//.aclr(!Hdmi_vde),
.aclr(Hdmi_Vsync),
.data(FIFO_WData),
.rdclk(clk_read),
.rdreq(Fifo2_rdreq),
.wrclk(clk_write),
.wrreq(FIFO_WR),
.q(Fifo2_q),
.wrusedw(Fifo2_wrusedw)
);



always @ (posedge clk_write)
FIFO_Full <= Fifo2_wrusedw[6];
reg [2:0] ccd_de_cnt;
always @(posedge clk_read or negedge resetn)
if(!resetn)
  ccd_de_cnt <= 3'b000;
else if (!Hdmi_De)
  ccd_de_cnt <= 3'b000;
    else if ((ccd_de_cnt == 3'b001) && Hdmi_De)//tangate 加上的，原先没有
        ccd_de_cnt <= 3'b000;//tangate 加上的，原先没有
else if(Hdmi_De)
  ccd_de_cnt <= ccd_de_cnt + 1'b1;
  
always @(*)
if (ccd_de_cnt == 3'b000 && Hdmi_De)
  Fifo2_rdreq <= 1'b1;
else
  Fifo2_rdreq <= 1'b0;
  
reg Fifo2_rdreq1;
always @(posedge clk_read or negedge resetn)
if(!resetn)
  Fifo2_rdreq1 <= 1'b0;
else
  Fifo2_rdreq1 <= Fifo2_rdreq;

reg [63:0] fifo_rdata;
always @(posedge clk_read or negedge resetn)
if(!resetn)
  fifo_rdata <= 64'h0;
else if (Fifo2_rdreq1)
  fifo_rdata <= Fifo2_q;
else if(Hdmi_De)
  fifo_rdata <= fifo_rdata >> 32;//tangate 原先为8

assign de_out = de_delay[13];//29
reg [29:0] de_delay;
always @(posedge clk_read)
begin
if(!resetn)
  de_delay <= 30'b0;
else
  de_delay <= {de_delay[28:0],Hdmi_De};
end
always@(posedge clk_read)
begin
if(Hdmi_De)
begin
   data_out <= fifo_rdata[31:0];
end
else
data_out<=32'h00;
end


endmodule

czjcz11

这个很简单的呀。。。

duan_dzj

没有看懂！