freecale 上海 ic类职位招聘

lyonel

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职位描述如下：

►数字前端

IP Frontend Design & Verification Engineer

Job Description
-   Logic design, implementation & verification by verilog for IPs and SOC  
development.
-   Participate in the complex SoC design project based on arm cores at  
advanced technology, complete the task assignment on time with good quality.
-   Testbench generation, verification test pattern development and  
simulation on module/chip level,  using Verilog, System Verilog, C/C++ and  
other verification languages.
-   Participate in logic synthesis, DFT, timing analysis and closure.
-   Independently solve technical issues and find the solutions.
-   Write the technical documents/papers as required.
-   Cooperate with and provide support to other functional teams  
(S&A,SW,TE/PE) in the NPI execution.
  
Qualifications  
  
-          Bachelor, Master or above on Electronics, Communications,  
Microelectronics Engineering and Computer Science.  
-          Bachelor with 2+ years or master with 1+experience in digital  
design based on high-level languages with good knowledge of IC design flow,  
including coding, simulation, verification, synthesis, DFT and STA.  
-          Familiar with the main EDA tools, such as from Cadence, Synopsys  
and Mentor, and their related methodology/flow.  
-          Familiar with high speed serial bus or display/sensor such as  
USB/HDMI/MIPI is a plus.
-          Relevant experience on ARM, MCU/dsp based SOC design for  
multimedia, wireless communication and consumer areas is a plus.  
-          More years of relevant work experience will be considered as Sr.  
position.





SOC Frontend Design Engineer

Job Description
-   Participate in the complex SoC design project based on ARM/DSP cores at  
advanced technology, complete the task assignment on time with good quality.
-   Logic design & implementation by Verilog for IPs and SOC development.
-   Testbench generation, verification test pattern development and  
simulation on module/chip level,  using Verilog, System Verilog, C/C++ and  
other verification languages.
-   Participate in logic synthesis, DFT, timing analysis and closure.
-   Independently solve technical issues and find the solutions, master on  
several areas.
-   Write the technical documents/papers as required.
-   Cooperate with and provide support to other functional teams  
(S&A,SW,TE/PE) in the NPI execution.
-   Independently solve technical issues and provide guidance to junior  
members.
  
Qualifications  
  
-          Bachelor, Master or above on Electronics, Communications,  
Microelectronics Engineering and Computer Science.  
-          Bachelor with 3+ years or master with 2+experience in digital  
design based on high-level languages with good knowledge of IC design flow,  
including coding, simulation, verification, synthesis, DFT and STA.  
-          Familiar with the main EDA tools, such as from Cadence, Synopsys  
and Mentor, and their related methodology/flow.  
-          Relevant experience on ARM, MCU/DSP based SOC design for  
multimedia, wireless communication and consumer areas is a plus.  
-          Additional hands-on experience on FPGA prototyping, SOC system  
definition, advanced verification, silicon validation and low power design is  
a big plus.  
-          More years of relevant work experience will be considered as Sr.  
position.




►数字后端
Senior IC design backend engineer

Responsibility:
1.    Work with the global design team to do complex SOC physical  
implementation for deep submicron design.  
2.    Participates in chip level and block level backend design for complex  
SOC designs.
3.    Responsible for RTL to GDS flow including CPF definition,  
logic/physical synthesis, die size estimation, floor-planning, power  
planning, CTS, place and route, STA, signal integrity, timing closure, formal  
verification, DFM, DRC/LVS etc.
4.    Play a critical role in high performance design timing closure.
Qualifications:
1.    University degree in microelectronics engineering or equivalent,  
master degree or above is preferred;
2.    5+ years industry experience, at least 3 years in physical design  
role in submicron projects;
3.    Good understanding on backend flow and process, special for partition  
flow;
4.    Successful completion of 5+ physical design projects  (at least one  
at 65nm or below);
5.    Experience on Cadence, Synopsys, Magma, Mentor tools;
6.    Hands on experience on floorplan, place and route, STA, IR drop and  
signal integrity,  DRC/LVS;
7.    Hands on experience on synthesis is preferred;
8.    Good communication skills is must, English language proficiency.



►部门介绍
Freescale’s Networking & Multimedia Group (NMG) is enabling a new area of  
networking where every connection matters — making connections that keep you  
in touch with anyone, at any time, anywhere on any device. NMG serves  
manufacturers of home networking equipment, enterprise networking solutions,  
infrastructure equipment and pervasive computing products with our leading  
PowerQUICC® communications processors, QorIQ™ communications platforms and  
StarCore® digital signal processors (DSPs). Through NMG, Freescale has  
achieved industry recognition as the No. 1 supplier of communications  
processors. In addition, the group's comprehensive multimedia portfolio,  
which includes multimedia applications processors based on ARM® core  
technology and Symphony™ DSPs, deliver rich experiences — whether it is in  
portable consumer devices, automotive infotainment or a variety of  
audio/video equipment. With a deep understanding of emerging markets and end-
customer requirements, NMG delivers comprehensive system-level solutions  
backed by software, development tools and reference designs. These solutions  
help customers reduce costs, ease migration to next-generation designs and  
drive rapid market acceptance of their products.

     
Please visit the below link for more information:
http://www.freescale.com.cn/

hitten

貌似我符合条件，不知道多少米？