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本帖最后由 ukinfo 于 2012-7-25 17:14 编辑
As you know Functional Verificaion and also ESL Dessign are the most intersting and important parts of these days complex SOC designs. They are 5 jaint EDA tools that support these:
1- Aldec Riviera & Active-HDL
2- Cadence Incisive
3- Novas Vedri
4- Mentor Modelsim & Questasim
5- Synopsys VCS
=======================
All of them have common capabilities but some ones are unique and also some of them have features that can be integrated only with their internal products.
I love Riviera because of it has very nice GUI and also power in handeling with large designs and also it's very beautiful waveform window and lots of features. If you work with that you will never put that away. Don't believe just try, but don't forget to share that.
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http://www.aldec.com/en/products/functional_verification/riviera-pro
Brochure:
http://www.aldec.com/files/products/Riviera-PRO_Brochure.pdf
------------------------------- - Advanced Verification Platform (UVM/OVM, VMM)
- Different Levels of Abstraction (ESL/TLM, RTL, Gate-Level)
- High-Performance Simulator for Mixed Language Designs
- IEEE VHDL, Verilog®, SystemVerilog, SystemC/C/C++
- Transaction-Level Debugging Environment
- Assertion-Based Verification (SVA, PSL and OVA)
- Code and Functional Coverage
- DSP Co-Simulation with MATLAB® and Simulink®
- Linux and Windows® 7/2008/Vista/XP/2003 32/64 Bit Support
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发表于 2012-7-11 17:50:35
