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楼主 |
发表于 2012-6-23 20:10:52
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再给一个新open的job JD：
Sr/MTS Low Power DV engineer：
Position Summary
In this key role, the candidate will be responsible for low power implementation and verification of hardware.
Requirements/Qualifications:
• BS, MS or PhD in Computer Science or Electrical Engineering.
• 3+ (or 6+ for MTS and above) years of ASIC verification or low power design experience
• Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release.
• Advanced programming knowledge on Verilog/SystemVerilog, C/C++
• Requires demonstrated technical expertise in the areas of Design Verification and low power design/verification methodology.
• Knowledge on Perforce, OVL, SVA, SV, UVM, script programming etc.
• Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically. |
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eetop公众号
创芯大讲堂
创芯人才网
发表于 2012-6-18 14:59:59
