spice vision => read spice convert to schematic ..
like cadence virtuoso composer cdl in (spice in)
gate vision =-> reading verilog gate netlist
rtl vision => rtl code , like debussy
Spice vision => spice netlist 转成电路 Gate vision => 读VERILOG NETLIST , 要先弄好 STD_cell symbol 就可读出来 RTL => debussy 早期有看RTL 会生成FSM 等 ..
https://bbs.eetop.cn/thread-923156-1-1.html
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