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module Dif (dif,a,h,clock);
output [31:0] dif;
input [31:0] a,h;
input clock;
wire [31:0] x1,x2,y1,y2,divident,divisor;
add M1 (
.clock (clock),
.dataa (a),
.datab (h),
.result (x1));
sub M2 (
.clock (clock),
.dataa (a),
.datab (h),
.result (x2));
Exp M3 (
.clock (clock),
.data (x1),
.result (y1));
Exp M4 (
.clock (clock),
.data (x2),
.result (y2));
sub M5 (
.clock (clock),
.dataa (y1),
.datab (y2),
.result (divident));
mult_2 M6 (
.data (h),
.result (divisor));
div M7 (
.clock (clock),
.dataa (divident),
.datab (divisor),
.result (dif));
endmodule
被调用的模块
module Exp (
clock,
data,
result);
input clock;
input [31:0] data;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
Exp_altfp_exp_alc Exp_altfp_exp_alc_component (
.clock (clock),
.data (data),
.result (sub_wire0));
endmodule
错误
Error: Port "clock" does not exist in primitive "Exp" of instance "M3"
Error: Port "data" does not exist in primitive "Exp" of instance "M3"
Error: Port "result" does not exist in primitive "Exp" of instance "M3" |
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