AMD上海研发中心招聘工程师-HR直招

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AMD上海研发中心招聘工程师，该职位有机会接触并学习AMD最新的显卡技术和融合技术，请感兴趣的人务必以“所应聘职位_姓名_公司__学历_工作年限” 为标题，

把简历以附件形式发送到Maggie1.Zhang@amd.com,并说明应聘理由。

1.GPU Compute Architect (Engineer of Graphics Performance Verification)
- Write test plan for new graphics chips - Write performance tests for new graphics chips - Debug/Analysis performance bugs of graphics chips - Debug function bugs for performance tests - Write performance analysis tools for new graphics chips - Function verification for new features of graphics chips - Write benchmarks for new graphics chips - GPGPU performance verification	More than 5 years’ experience with one of following: - Software: OGL/D3D driver background - 3D/GPU Architecture - IC Design/verification Background - GPU design/verification - 3D Application programming etc. - Compiler Back Ground - Graphics Architecture - GPGPU related jobs
2.Section Manager of Graphics Verification
- As a design verification section manager, leading the SHG GC DV team, working with the architects in Graphics area and experienced designers to develop the graphics pipeline in GPU, ensure the delivery of high-quality GPU chip. - Essential Functions: - Managing the Graphics Verification team of a staff of 8-10 engineers in Shanghai. The tasks including verifying the functions for graphics pipeline for multiple GPUs and APUs. - Working closely with NA teams in Boston/Orlando/Sunnyvale -	- A minimum of M.Sc in Computer Science or EE or equivalent. . Preferably an advanced Computer Science or Engineering degree(Ph.D.) - 5+ years of experience in Graphics pipeline design/verification or 3D application development - More than 1 year of experience in technical lead - Solid understanding of the graphics algorithm - Good leadership skills and strong communication skills (English and Mandarin, both written and verbal) - Good team work skills - Passion to work efficient and improve the current methodology - Must work well under pressure and have the ability to multi task effectively
3. MTS Design Verification Engineer for Graphics Hardware
- Understand the architecture of the chip and functional block being designed - Compose test plan and validation vectors to ensure functional completeness - Develop verification environments for standalone unit testing and enhance/use the automated regression infrastructure setup for unit level, IP level and full chip functional verification. - Help debug and correct functional errors in the design blocks, using logic abstraction, simulation and debug tools, based on good understanding of the architectural specification, RTL and/or device level design of the block. - Closely working with Design/Architecture/Circuit team to identify the Milestones and Quality metrics of the project that includes scoping, tracking and delivery. - Be responsible to mentor and coach the team for greater technical depth in Functional areas as well as the verification methodology improvement and Infrastructure enhancements to support the design environment -	- Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences - Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification - Needs to have better understanding of Verification methodology and concepts. - Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release. - Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically. - Familiar with Linux Environment (including shell scripting and linux gnu tools) - Advanced programming knowledge on Verilog,C++ - Design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.) - Strong problem solving skills -
4. Sr./MTS Engineer of GFX Design Verification
- Creativity. AMD is the underdog in the CPU wars. Intel is able to outspend them, and it is therefore important that the company be creative and aggressive in the use of its marketing dollars. - Ability to deal with complexity. This is one of the most complex marketing jobs that exist. Consumers, corporate accounts, retailers, channels, system integrators, the government and PC manufacturers both very large and very small must all be influenced. There are many ways in which AMD can spend its money; distilling this complexity down to the key issues and executing on them is critical. - Tenacity. Individuals who aspire to an easy life in a company with a dominant position will struggle in this role. Although AMD has many allies, and the desire among all parties for an alternative to Intel is very strong, the fact is that the company is an underdog. While this is clearly an opportunity to perform, it will require a strong will to deal with setbacks. - Leadership. The ability to bring the team together, motivate them to do battle, and to bring the best ideas to the surface is essential. - Business Savvy. This is a key leadership role in Greater China and the individual is likely a candidate to succeed the General Manager role in due course and has to demonstrate a very high degree of business acumen. -	- Has 1-2 (Sr.) or 3-5 (MTS) year of experience on OpenGL/OpenCL/Cuda/D3D programming - Deeply understands the graphics pipeline, interesting in the verification work for graphics pipeline. - Has Zeal for knowledge inside the Graphics Core - Has knowledge of DX9-DX12 is an option - Has experience in algorithm modeling for Graphics Core is an option. - Has good experience in shader programming is an option - Familiar with C/C++ programming is a must - Familiar with one of the following language : System Verilog, System C, OVM, UVM - Familiar with Verilog, VHDL is an option. - Familiar with Perl or any other script language is an option. - Good at both Oral and written English - Willing to take responsibilities and learn new things. - Good at communication and Team work. -
5. MTS ASIC CAD Engineer - DFP
- Be part of DFP CAD. His responsibilities will include: - - Flow development for DFP using Icc initially then broaden to all tools used in tile level flows - - Developing and delivering training for local PD team focused on - o Power aware floorplanning - o Power aware verification (MVRC/Formality/CLP) - o Power closure (leakage opt/cts optimization) - - Taking on project level responsibilities in crunch time as expert help - o Eco support - o Scripting for Icc -	- Major in EE, CS or related, Master Degree with 6+ years or Bachelor with 8+ years working experiences - Extensive Back-end (PD) flow skill - Familiar with ICC and other back-end tools usage. - Have strong scripting skill. - Have experience Power Aware floorplaning, verification and power closure is preferred. - Analytic skills and problem solving skills - Good communication skill - Fluent English in both oral/written -
6.Sr. Design Engineer for GPU IP
- Develop micro-architecture for GPU blocks based on architectural requirement. - Develop RTL code for GPU blocks in Verilog HDL and make sure functional correct and reusable for different configuration. - Synthesis and deliver netlist that meeting timing, area and power requirement. Help PD on the floorplanning and close timing. -	- MS degree of EE with 5+ years working experience in ASIC Company.   - Expert of Verilog RTL design and has experience of large digital ASIC project. - Familiar with front-end EDA tools and flows. - Familiar with C/C++ programming and unix/linux and scripts (tcl, perl etc.) - Fluent English on talking, presentation and writing documents.   - Work is performed with limited supervision. Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager. - Can solves complex, novel and non-recurring problems; initiates significant changes to existing processes/methods and leads development and implementation - Possesses specialized knowledge of Computer architecture and computer arithmetic - Possesses specialized knowledge of Computer graphic knowledge -
7.MTS Verification Infrastructure Engineer for Graphics IP
- Design Verification Engineer for Graphics IP, being responsible for Front-end verification methodology, test bench and infrastructure of the Graphics IP. - Participate in the research of Design Methodology to improve automation and productivity to produce AMD's new high-quality cutting-edge graphics processing products - Deploy the advanced verification methodology and infrastructure of the Graphics IP - Interface with the global Graphics IP teams and Central Verification groups. - Technical support -	- Major in EE, CS or related, Master Degree with 5+ years or Bachelor with 7+ years working experiences - Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM, UVM etc as well as knowledge of industry standard tools for verification - Needs to have better understanding of Verification methodology and concepts. - Should have good understanding of Pre-Silicon design process from Architecture, Design, Synthesis and Gate level Implementation till Tapeout release. - Should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically. - Familiar with Linux Environment - Advanced programming knowledge on Ruby, Perl, Verilog/SystemVerilog, C/C++ - Design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.) - Strong problem solving skills -
8. Sr./MTS Verification Engineer for ECOE
- This position is for a verification engineer in AMD's Emulation Center of Expertise (ECOE) group working on next generation high performance graphics (GPU) and APU architectures in the hardware emulator team. - Hardware emulation model creation and deployment - Pseudo-Silicon bring up on hardware emulator - Test plan development, scheduling, writing, and debug. - Supporting/engaging with the design and software teams -	- BS/MS in EE, CS, CSE plus a minimum 5 years hardware verification experience - Experience with Verilog, C/C++, Perl required - Experience with Hardware Emulator systems a plus - Background and interest in computer graphics a plus - Candidates should have experience contributing to hardware verification throughout the full production cycle, from architecture to tape out. - Candidates should have excellent communication skills (both written and oral) and should be able to participate cross functional engineering teams geographically. - Candidate must be able to work in a close knit team and take on different tasks depending upon the need on the project at a particular time. - Candidates should have strong problem solving skills -
9.Sr. /MTS Engineer of Physical Design
- Work with global Front-End design team and physical design team for large scale ASIC chip physical implementation. Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc. The individual is expected to be an expert in multiple aspects in PD areas and provide technically leadership to the engineering team. The individual is also expected to be accountable for project delivery. -	- MSEE with 8+ years or Bachelor with 10+ years of industrial experience in ASIC design - 5+ years or more years of experience in physical design of deep submicron digital ASIC chips - Hands on experience in large scale ASIC chip physical design - Knowledgeable in all aspects of deep submicron ASIC design flow - Successfully gone through several complete product development cycles - Demonstrate strong leadership and work well with cross-functional teams - Good listening, writing and speaking English - Good communication skills, strong interpersonal skills and the flexibility - Dedicated, hard working and good team player - Familiar with Back-End (physical design) EDA tools - Familiar with Front-End EDA tools is a plus - Familiar with Unix/Linux environment and good at scripts -
10.Senior/Staff GPU Integration Engineer
- Define GPU chip level specification, including clock and power targets, IP selection, floorplan review, package definition, PCB spec etc. - Estimate GPU performance and TDP before ASIC bring-up. Provide regarding information to make up test plans. - Communicate with design and marketing teams to define bounding-box for SKU volumn split. - Bring-up ASIC. Guide hardware team to solve design problem in application. Help to short Time-To-Market. -	- MS degree of EE with more than 5 years working experience in ASIC Company.   - Familiar with Verilog RTL design and has experience of large digital ASIC project. - Experience for ASIC tapout and bring up. - Fluent English on talking, presentation and writing documents.   - Strong sense of task scheduling and deliver on time as predetermined milestones committed to manager. -