Verification Methodology Manual.3rd.Edition ，自制PDF

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Content
Foreword8
About the authors8
Acknowledgements9
Preface10
Overview of Front-End Tools12
Circuit Design Can Be A Risky Business12
The Front to Back Design Route12
Handling Design Changes15
Summary17
Chapter 218
Code and Rule Checking in the Design Flow18
hdl Capture Tools18
Text Editors18
Linters19
Graphical Editors19
Rule-based Checkers20
Rule Checking and the Design Hierarchy22
Chapter 326
Introduction to Coverage Analysis26
The Origins of Coverage Analysis26
Applying Coverage Analysis Techniques to HDL27
Modern Hardware Design Tools27
Typical Capabilities of Coverage Analysis Tools28
How Coverage Analysis Tools Operate29
Analyzing the HDL source code29
Collecting coverage data from the simulation30
Presenting the results to the user30
Command Line and Batch Mode31
Chapter 432
Coverage Analysis in the Design Flow32
Current asic Design flow32
Coverage Analysis in the Design Flow35
IP in the Design Flow38
Chapter 540
Practical Value of Coverage Analysis40
HDL Verification Problem40
Coverage Analysis and HDL Verification41
Project Management With Coverage Analysis42
Functional Coverage42
Regression Testing43
Gate Level Testing43
Chapter 645
Coverage Analysis Measurements45
Structural and Functional Testing45
Statement Coverage46
Branch Coverage48
How Branch Coverage is Calculated49
Condition and Expression Coverage50
Multiple Sub-Condition Coverage51
Basic Sub-Condition Coverage51
Directed or Focused Expression Coverage (FEC)52
Path Coverage55
Toggle Coverage57
Triggering Coverage59
Signal Tracing Coverage61
Dealing with Information Overload62
Excluding Code65
Post-Simulation Results Filtering66
Summary70
Chapter 771
Coverage Directed Verification Methodology71
Coverage Analysis in the Design Flow71
Coverage Analysis at Behavioral Level71
Coverage Analysis at RTL72
Coverage Analysis and Transient Behavior74
Coverage Analysis at Gate Level75
Coverage Analysis and State Machines76
Practical Guide Lines for Coverage Analysis77
Coverage Analysis as a Verification Advisor79
Coverage Measurements and Targets79
Saving Simulation Time81
Number of Coverage Analysis Licenses Required82
Chapter 884
Finite State Machine Coverage84
FSM Coverage84
FSM Path Coverage84
Reachability Based Path Extraction85
Manual Path Specification86
TransEDA''s FSM Path Approach86
Focus On Functionality87
Supercycle 187
Supercycle 288
Supercycle 388
Simplify Complexity89
A Complex Example90
Conclusion92
Cycles Automatically Extracted by VN-Cover93
Manually Created Paths for Tap Controller96
Chapter 999
Dynamic Property Checking99
Structural Testing99
Visual Checking100
Self-Checking Test Benches100
Pattern Matching100
Properties101
Verification Flow101
Dynamic Property Checking in Operation103
Collecting Simulation Results103
Typical method of implementation105
Chapter 10109
Verification Architecture for Pre-Silicon Validation109
Introduction109
Pre-silicon Validation110
Concurrency111
Automated Test Generation111
Robust, High-quality Verification IP112
Ease of Use113
Leveraging Design and Application Knowledge113
Right Level of Abstraction114
Debugging114
Configurability114
Reusing the Test Environment114
Machine Cycles Become Less Expensive114
An Architecture for Pre-silicon Validation115
Verification components116
Intelligent Bus Functional Models116
Intelligent Bus Protocol Monitors116
Intelligent Test Controller and Data Checker116
Conclusion116
Chapter 11118
Overview of Test Bench Requirements118
Basic Test Bench Construction118
Coverage Directed Test Benches119
Test Bench for a Single Module or Single Unit120
Dealing with Multiple Test Benches121
Improving Your Testing Strategy122
Writing Test Benches - Functional Verification of HDL Models123
Chapter 12124
Analyzing and Optimizing the Test Suite124
The Test Suite124
Regression Testing126
Merging Test Bench Results128
Optimizing the Test Benches128
Identifying Test Benches for ECO131
Appendix A134
On-Line Resources and Further Reading134
Coverage Analysis Tools134
Verification Navigator135
Design Rule Checker135
verilog and VHDL Simulators135
Verilog135
VHDL136
ModelSim Simulator136
Verilog Source Files136
VHDL Source Files136
References for Further Reading136
Reuse Methodology Manual for System-on-a-chip Designs136
Writing Test benches - Functional Verification of HDL Models137
HDL Chip Design137
Appendix B138
HDL Checking - Worked Examples138
Getting Organized138
Starting the Rule-Based Checker138
Selecting a Rule Database139
Selecting the Run Options141
Running the Rule-Based Checker141
Viewing the Results142
Editing the Source Files144
Appendix C146
Verilog Coverage Analysis - Worked Examples146
Getting Organized146
Directory and File Structure146
Command Line Batch File147
Parameter File (Global and Local)148
Collecting Coverage Results148
Viewing Coverage Results149
Appendix D159
VHDL Coverage Analysis - Worked Examples159
Getting Organized159
Directory and File Structure159
Getting The Results160
Appendix E169
FSM Coverage - Worked Examples169
Directory and File Structure169
Command Line Batch File169
Collecting Coverage Results170
Viewing Coverage Results171
State Coverage175
Arc and Path Coverage176
State Diagram176
Cycle Information177
Appendix F179
Dynamic Property Checking - Worked Examples179
Resources179
Directory and File Structure179
Command Line Batch File179
Description of the Design180
Collecting Coverage Results180
Viewing Coverage Results181
Appendix G188
Creating Properties - Worked Examples188
Getting Organized188
Background188
Overview189
Circular Tour190
Looping on S2191
Counting the number of loops191
Matching two lower level sequences191
Using a Signals file191
A glossary of EDA and CAE terms200
An index of topics in this book206

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shenbiao

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Zyson

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freelion

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mingrenyc

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