ADC中电容类型的选择

fuyibin

回复  fuyibin


    我依稀记得原来用过的.6的工艺的PIP的介质大约400A左右，属于氧化和淀积均可的厚度 ...
ericking0 发表于 2012-5-5 08:56

                               
登录/注册后可看大图

40nm用氧化做比较难了，要么湿氧生长，干氧估计长不到那么厚
而且poly上生长氧化层不知道好不好
事实上MOM cap要比PIP和MIM电容都好，而且好很多......

小飞侠111

回复 20# ericking0


   我问过使用过这个工艺的人了，他们都用pip的。

ericking0

回复 22# 小飞侠111


    那么就用呗，多花了一层mask的钱，面积又小些，精度高些，不用白不用

peterlin2010

在 0.5um  only PIP  , double poly ..
0.5um 40v process  多用 PIP .
新的 process 多改 mim ..但 mim 一樣多層MASK  把MIM 讓IMD變薄 ..
0.35um 0.25  0.18 多用 MIM
MIM  or PIP 都是低壓因為要電容大 間距要小, Breakdown 會差..

MOS CAP一般是 mim  or pip  3倍左右 ..
選 mim or PIP 是 fab process 先選好的 ..不是你想用就能用的 ..

不知 90nm 65nm 下 analog 是那類 ??

fhchen2002

回复 1# 小飞侠111

Based on the description of the models,
Capacitance per unit area: MIM = PIP
Standard deviation per unit area: MIM = PIP

In terms of accuracy and needed silicon area, both types of capacitor have the same performance.

MIM: bottom plate at least needs to use M2 -> about 2.7-µm distance from M2 to substrate
PIP: bottom plate is POLY1 about 6000 -> about 0.32-µm distance (i.e., thickness of FOX / STI oxidie) from poly1 to substrate

Conclusion:
PIP suffers significantly more parasitic capacitance from bottom plate to substrate

fhchen2002

回复 24# peterlin2010


For 90 nm / 65 nm CMOS process technogies, since the totla number of interconnect layers (i.e., metal layers) is large (>= 6), MOM can be used.

MOM (Metal-Oxide-Metal)
Meta-to-metal, same layer + metal-to-metal different layers, from M2 to M-top.

peterlin2010

If I need hi voltage cap ?? like sample/hold circuit .. some high voltage like regulator also
need Hi -volt cap , we usually use hi-V nmos cap , but nmos Gate oxide is "large" ..

istart_2002

看到楼主的帖子上面写的是关于pipcap的mismatch model，不知道这个是楼主自己写的还是工艺文件里面本来就有的呢，用这个跑monte carlo仿真能给仿出波形来吗

tianzhiya

这个一般用mim用得多一些吧

junw2

MIM is not the most accurate, but the most linear, and less parasitics because it is on the top of the die. Matching is also better.