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我在Ubuntu10.10上装了VCS2009.6 网上很多人都说能运行,我装完之后DVE能正常启动。。。
但是我在网上找了一个4位加法器的Verilog文件和他的testbanch 文件分别为add。v和top。v
然后进行编译出现duhanyu@ubuntu:~/synopsys$ vcs top.v add4.v
Chronologic VCS (TM)
Version C-2009.06 -- Thu Apr 5 12:01:32 2012
Copyright (c) 1991-2008 by Synopsys Inc.
ALL RIGHTS RESERVED
This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.
Parsing design file 'top.v'
Parsing design file 'add4.v'
Top Level Modules:
top
No TimeScale specified
Starting vcs inline pass...
1 module and 0 UDP read.
However, due to incremental compilation, no re-compilation is necessary.
gcc -pipe -O -I/home/duhanyu/synopsys/vcs/vcs/include -c -o rmapats.o rmapats.c
if [ -x ../simv ]; then chmod -x ../simv; fi
g++ -o ../simv 5NrI_d.o 5NrIB_d.o N654_1_d.o rmapats_mop.o rmapats.o SIM_l.o /home/duhanyu/synopsys/vcs/vcs/linux/lib/libvirsim.a /home/duhanyu/synopsys/vcs/vcs/linux/lib/librterrorinf.so /home/duhanyu/synopsys/vcs/vcs/linux/lib/libsnpsmalloc.so /home/duhanyu/synopsys/vcs/vcs/linux/lib/libvcsnew.so /home/duhanyu/synopsys/vcs/vcs/linux/lib/vcs_save_restore_new.o /home/duhanyu/synopsys/vcs/vcs/linux/lib/ctype-stubs_32.a -ldl -lc -lm -lpthread -ldl
../simv up to date
CPU time: .032 seconds to compile + .008 seconds to elab + .300 seconds to link
duhanyu@ubuntu:~/synopsys$
请问这是我VCS的问题还是两个文件的问题呢?怎么才能证明VCS安装成功了呢?
求指导 希望大家互相交流下 |
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