奇怪的cadence license问题

8i8i9o9o · 发表于 2012-4-2 13:33:11

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诸位大哥，
小弟的cadence 用的是floating license. 昨天还好好的
今天schematic就不能编辑了。报了下面的错误。
\w *WARNING* Unable to check out a Schematic Editor license (34500, Virtuoso_Schem_Option + 300, Virtuoso_Schematic_Editor_L or Virtuoso_Schematic_Editor_XL)
\w *WARNING* Schematic Editor: license file does not contain a license for feature 34500
\w *WARNING* Schematic Editor: license file does not contain a license for feature Virtuoso_Schem_Option
\w *WARNING* Schematic Editor: license file does not contain a license for feature Virtuoso_Schematic_Editor_L
\w *WARNING* Schematic Editor: license file does not contain a license for feature Virtuoso_Schematic_Editor_XL

但是查看lmgrd的log文件(下面)没看到什么错误呀。
其中34500表示已经运行了。那位高人指点一下。谢了！

16:27:50 (lmgrd) -----------------------------------------------
16:27:50 (lmgrd) Please Note:
16:27:50 (lmgrd)
16:27:50 (lmgrd) This log is intended for debug purposes only.
16:27:50 (lmgrd) In order to capture accurate license
16:27:50 (lmgrd) usage data into an organized repository,
16:27:50 (lmgrd) please enable report logging. Use Macrovision's
16:27:50 (lmgrd) software license administration  solution,
16:27:50 (lmgrd) FLEXnet Manager, to  readily gain visibility
16:27:50 (lmgrd) into license usage data and to create
16:27:50 (lmgrd) insightful reports on critical information like
16:27:50 (lmgrd) license availability and usage. FLEXnet Manager
16:27:50 (lmgrd) can be fully automated to run these reports on
16:27:50 (lmgrd) schedule and can be used to track license
16:27:50 (lmgrd) servers and usage across a heterogeneous
16:27:50 (lmgrd) network of servers including Windows NT, Linux
16:27:50 (lmgrd) and UNIX. Contact Macrovision at
16:27:50 (lmgrd) www.macrovision.com for more details on how to
16:27:50 (lmgrd) obtain an evaluation copy of FLEXnet Manager
16:27:50 (lmgrd) for your enterprise.
16:27:50 (lmgrd)
16:27:50 (lmgrd) -----------------------------------------------
16:27:50 (lmgrd)
16:27:50 (lmgrd)
16:27:50 (lmgrd) The license server manager (lmgrd) running as root:
16:27:50 (lmgrd)    This is a potential security problem
16:27:50 (lmgrd)    and is not recommended.
16:27:50 (lmgrd) FLEXnet Licensing (v10.8.5.0 build 31891 i86_re3) started on core8 (linux) (4/1/2012)
16:27:50 (lmgrd) Copyright (c) 1988-2006 Macrovision Europe Ltd. and/or Macrovision Corporation. All Rights Reserved.
16:27:50 (lmgrd) US Patents 5,390,297 and 5,671,412.
16:27:50 (lmgrd) World Wide Web:  http://www.macrovision.com
16:27:50 (lmgrd) License file(s): /tools/cadence/license.dat
16:27:50 (lmgrd) lmgrd tcp-port 5280
16:27:50 (lmgrd) Starting vendor daemons ...
16:27:50 (lmgrd) Started cdslmd (internet tcp_port 32791 pid 6182)
16:27:50 (cdslmd) FLEXnet Licensing version v10.8.6.0 build 54361 i86_re3
16:27:50 (cdslmd) EXPIRED: Envisia_PKS
16:27:50 (cdslmd) EXPIRED: Envisia_SE_ultra_place_route
16:27:50 (cdslmd) EXPIRED: Silicon_Ensemble_DSM
16:27:50 (cdslmd) EXPIRED: FirstEncounter
16:27:50 (cdslmd) EXPIRED: FirstEncounterSOC
16:27:50 (cdslmd) EXPIRED: FE_Classic
16:27:50 (cdslmd) EXPIRED: FE_Ultra
16:27:50 (cdslmd) EXPIRED: SOC_Encounter
16:27:50 (cdslmd) EXPIRED: Encounter_C
16:27:50 (cdslmd) EXPIRED: Envisia_SE_SI_place_route
16:27:50 (cdslmd) EXPIRED: NanoRoute_Ultra
16:27:50 (cdslmd) EXPIRED: Nano_Encounter
16:27:50 (cdslmd) EXPIRED: RTL_Encounter
16:27:50 (cdslmd) EXPIRED: Encounter_ClockSyn
16:27:50 (cdslmd) EXPIRED: RTL_Compiler_Ultra
16:27:50 (cdslmd) EXPIRED: FE_GPS
16:27:50 (cdslmd) EXPIRED: SOC_Encounter_GPS
16:27:50 (cdslmd) Server started on core8 for: 100
16:27:50 (cdslmd) 111       11400       12141
16:27:50 (cdslmd) 12500       14000       14010
16:27:50 (cdslmd) 14020       14040       14101
16:27:50 (cdslmd) 14111       14120       14130
16:27:50 (cdslmd) 14140       14410       200
16:27:50 (cdslmd) 20120       20121       20122
16:27:50 (cdslmd) 20123       20124       20127
16:27:50 (cdslmd) 20128       20220       20221
16:27:50 (cdslmd) 20222       20227       206
16:27:50 (cdslmd) 207       21060       21200
16:27:50 (cdslmd) 21400       21900       21920
16:27:50 (cdslmd) 22650       22800       22810
16:27:50 (cdslmd) 24015       24025       24100
16:27:50 (cdslmd) 24205       250       251
16:27:50 (cdslmd) 26000       274       276
16:27:50 (cdslmd) 279       283       300
16:27:50 (cdslmd) 305       312       314
16:27:50 (cdslmd) 316       318       32110
16:27:50 (cdslmd) 32140       32150       32190
16:27:50 (cdslmd) 322       32500       32501
16:27:50 (cdslmd) 32502       32510       32550
16:27:50 (cdslmd) 32600       32610       32620
16:27:50 (cdslmd) 32630       32640       32760
16:27:50 (cdslmd) 33010       33301       334
16:27:50 (cdslmd) 336       34500       34510
16:27:50 (cdslmd) 365       370       371
16:27:50 (cdslmd) 37100       373       40020
16:27:50 (cdslmd) 40030       40040       40500
16:27:50 (cdslmd) 41000       50000       50010
16:27:50 (cdslmd) 501       50110       50200
16:27:50 (cdslmd) 51022       51023       51060
16:27:50 (cdslmd) 51070       51170       550
16:27:50 (cdslmd) 570       61300       61400
16:27:50 (cdslmd) 71110       71120       71130
16:27:50 (cdslmd) 920       940       945
16:27:50 (cdslmd) 950       960       963
16:27:50 (cdslmd) 964       965       966
16:27:50 (cdslmd) 972       974       991
16:27:50 (cdslmd) 994       995       ABIT
16:27:50 (cdslmd) ALL_EBD       AMD_MACH ANALOG_WORKBENCH
16:27:50 (cdslmd) AWB_BEHAVIOR AWB_Batch AWB_DIST_SIM
16:27:50 (cdslmd) AWB_MAGAZINE AWB_MAGNETICS AWB_MIX
16:27:50 (cdslmd) AWB_PPLOT AWB_RESOLVE_OPT AWB_SIMULATOR
16:27:50 (cdslmd) AWB_SMOKE AWB_SPICEPLUS AWB_STATS
16:27:50 (cdslmd) Actel_FPGA Advanced_Cell_Placer Advanced_Package_Designer
16:27:50 (cdslmd) Affirma_AMS_distrib_processing Affirma_NC_Simulator Affirma_NC_VHDL_Desktop_Sim
16:27:50 (cdslmd) Affirma_RF_IC_package Affirma_RF_SPW_model_link Affirma_advanced_analysis_env
16:27:50 (cdslmd) Affirma_equivalence_checker Affirma_sim_analysis_env Allegro_CAD_Interface
16:27:50 (cdslmd) Allegro_Designer Allegro_PCB_Interface Altera_MAX
16:27:50 (cdslmd) Ambit_BuildGates Ambit_libcompile Artist_Optimizer
16:27:50 (cdslmd) Artist_Statistics Atmel_ATV BOGUS
16:27:50 (cdslmd) Base_Digital_Body_Lib Base_Verilog_Lib BlockMaster_Characterizer
16:27:50 (cdslmd) BlockMaster_Optimizer BoardQuest_Team BuildGates_Extreme
16:27:50 (cdslmd) CELL3       CELL3_ARO CELL3_CROSSTALK
16:27:50 (cdslmd) CELL3_CTS CELL3_ECL CELL3_OPENDEV
16:27:50 (cdslmd) CELL3_OPENEXE CELL3_PA CELL3_PR
16:27:50 (cdslmd) CELL3_QPLACE_TIMING CELL3_SCAN CELL3_TIMING
16:27:50 (cdslmd) CELL3_WIDEWIRE CP_Ele_Checks CPtoolkit
16:27:50 (cdslmd) CWAVES       CWB01       CWB03
16:27:50 (cdslmd) CWB04       CWB05       CheckPlus
16:27:50 (cdslmd) Clock_Tree_Generation Cobra_Simulator ComposerCheckPlus_AdvRules
16:27:50 (cdslmd) ComposerCheckPlus_Checker ComposerCheckPlus_RuleDev Composer_EDIF300_Connectivity
16:27:50 (cdslmd) Composer_EDIF300_Schematic Composer_Spectre_Sim_Solution ConcICe_Option
16:27:50 (cdslmd) Corners_Analysis DISCRETE_LIB DRAC2CORE
16:27:50 (cdslmd) DRAC2DRC DRAC2LVS DRAC3CORE
16:27:50 (cdslmd) DRAC3DRC DRAC3LVS DRACACCESS
16:27:50 (cdslmd) DRACDIST DRACERC       DRACLPE
16:27:50 (cdslmd) DRACLVS       DRACPG_E DRACPLOT
16:27:50 (cdslmd) DRACPRE       DRACSLAVE Datapath_Preview_Option
16:27:50 (cdslmd) Datapath_VHDL Datapath_Verilog Device_Level_Placer
16:27:50 (cdslmd) Device_Level_Router Distributed_Dracula_Option EBD_edit
16:27:50 (cdslmd) EBD_floorplan EBD_power EDIF_Netlist_Interface
16:27:50 (cdslmd) EDIF_Schematic_Interface EMCdisplay EMControl
16:27:50 (cdslmd) Envisia_GE_ultra_place_route Envisia_RAC Envisia_Utility
16:27:50 (cdslmd) Envisia_LowPower_option Envisia_DataPath_option Extended_Digital_Body_Lib
16:27:50 (cdslmd) Extended_Digital_Lib Extended_Verilog_Lib FPGA_Flows
16:27:50 (cdslmd) FPGA_OPTIMIZER FPGA_Tools FUNCTION_LIB
16:27:50 (cdslmd) Framework GATEENSEMBLE GATEENSEMBLE_ARO
16:27:50 (cdslmd) GATEENSEMBLE_CROSSTALK GATEENSEMBLE_CTS GATEENSEMBLE_CTS_LE
16:27:50 (cdslmd) GATEENSEMBLE_CTS_UL GATEENSEMBLE_ECL GATEENSEMBLE_LOWEND
16:27:50 (cdslmd) GATEENSEMBLE_OPENDEV GATEENSEMBLE_OPENEXE GATEENSEMBLE_PA
16:27:50 (cdslmd) GATEENSEMBLE_PR_LE GATEENSEMBLE_PR_UL GATEENSEMBLE_QPLACE_TIMING
16:27:50 (cdslmd) GATEENSEMBLE_SCAN GATEENSEMBLE_TIMING GATEENSEMBLE_TIMING_LE
16:27:50 (cdslmd) GATEENSEMBLE_TIMING_UL GATEENSEMBLE_UNLIMITED GATEENSEMBLE_WIDEWIRE
16:27:50 (cdslmd) Gate_Ensemble_DSM Gate_Ensemble_DSM_Crosstalk Gate_Ensemble_WARP
16:27:50 (cdslmd) HDL-DESKTOP IC_Inspector IC_autoroute
16:27:50 (cdslmd) IC_edit       IC_hsrules IDF_Bi_Directional_Interface
16:27:50 (cdslmd) LAS_Cell_Optimization LEAPFROG-BV LEAPFROG-CV
16:27:50 (cdslmd) LEAPFROG-SLAVE LEAPFROG-SV LEAPFROG-SYS
16:27:50 (cdslmd) LID10       LID11       LINEAR_LIB
16:27:50 (cdslmd) LSE       MAG_LIB       MIXAD_LIB
16:27:50 (cdslmd) Model_Check_Analysis NCSim_Desktop NCVLOG_CGOPTS
16:27:50 (cdslmd) NC_Verilog_Compiler NC_Verilog_Data_Prep_Compiler NC_Verilog_Simulator
16:27:50 (cdslmd) NC_VHDL_Simulator NC-simulator Nihongoconcept
16:27:50 (cdslmd) OASIS_Simulation_Interface OpenModeler_SFI OpenModeler_SWIFT
16:27:50 (cdslmd) OpenSim       OpenWaves PICDesigner
16:27:50 (cdslmd) PIC_Utilities PLD       PWM_LIB
16:27:50 (cdslmd) Pearl       Pearl_Cell Placement_Based_Synthesis
16:27:50 (cdslmd) Prevail_Board_Designer Prevail_Correct_By_Design Prevail_Designer
16:27:50 (cdslmd) Preview_Synopsys_Interface QPlace       Quickturn_Model_Manager
16:27:50 (cdslmd) RapidPART SWIFT       Schematic_Generator
16:27:50 (cdslmd) SigNoiseCS SigNoiseEngineer SigNoiseExpert
16:27:50 (cdslmd) SigNoiseStdDigLib Signal_Integrity SiliconQuest
16:27:50 (cdslmd) SiliconQuest_CTGen_Option Silicon_Ensemble Silicon_Ensemble_CTS
16:27:50 (cdslmd) Silicon_Ensemble_DSM_Crosstalk Silicon_Ensemble_OpenDev Silicon_Ensemble_OpenExe
16:27:50 (cdslmd) Silicon_Ensemble_WARP Silicon_Synthesis_QPBS SimControl
16:27:50 (cdslmd) SimVision SpectreBasic SpectreRF
16:27:50 (cdslmd) Spectre_BTAHVMOS_Models Spectre_BTASOI_Models Spectre_NorTel_Models
16:27:50 (cdslmd) Spectre_ST_Models Substrate_Coupling_Analysis Synlink_Interface
16:27:50 (cdslmd) UET       ULMdelta ULMecho
16:27:50 (cdslmd) ULMhotel ULMindia ULMjuliette
16:27:50 (cdslmd) ULMmike       Universal_Smartpath VERILOG-SLAVE
16:27:50 (cdslmd) VERILOG-XL VERITIME VHDLLink
16:27:50 (cdslmd) VHDL_desktop VXL-ALPHA VXL-LMC-HW-IF
16:27:50 (cdslmd) VXL-SWITCH-RC VXL-TURBO VXL-VCW
16:27:50 (cdslmd) VXL-VET       VXL-VLS       VXL-VRA
16:27:50 (cdslmd) Vampire_HDRC Vampire_HLVS Vampire_MP
16:27:50 (cdslmd) Vampire_RCX Vampire_UI Verif_Ckpit_Analysis_Env
16:27:50 (cdslmd) Verilog_XL_Turbo_NT Verilog_XL_Desktop Verilog_desktop
16:27:50 (cdslmd) Virtuoso_Schem_Option Virtuoso_XL Xilinx_FPGA
16:27:50 (cdslmd) a2dxf       aae-signalscan aae-signalscan-transaction
16:27:50 (cdslmd) aae-transaction-explorer actomd       affirma-signalscan
16:27:50 (cdslmd) affirma-signalscan-control affirma-signalscan-pro affirma-signalscan-schmatic
16:27:50 (cdslmd) affirma-signalscan-source affirma-signalscan-transaction affirma-transaction-explorer
16:27:50 (cdslmd) allegro_dfa allegro_dfa_att allegro_non_partner
16:27:50 (cdslmd) allegro_symbol allegroprance archiver
16:27:50 (cdslmd) arouter       caeviews cals_out
16:27:50 (cdslmd) catia       cbds_in       cdxe_in
16:27:50 (cdslmd) comp       compose       compose_autoplan
16:27:50 (cdslmd) compose_gcr compose_scells compose_tlmr
16:27:50 (cdslmd) compose_util concept       conceptXPC
16:27:50 (cdslmd) cpe       cpte       crefer
16:27:50 (cdslmd) cvtomd       debug       dfsverifault
16:27:50 (cdslmd) dracula_in dxf2a       e2v
16:27:50 (cdslmd) edif2ged expgen       fethman
16:27:50 (cdslmd) fetsetup fluke       fsim
16:27:50 (cdslmd) gbom       ged2edif glib
16:27:50 (cdslmd) gloss       gphysdly gscald
16:27:50 (cdslmd) gspares       hp3070       iges_electrical
16:27:50 (cdslmd) intrgloss intrroute intrsignoise
16:27:50 (cdslmd) ipc_in       ipc_out       lwb
16:27:50 (cdslmd) mdin       mdout       mdtoac
16:27:50 (cdslmd) mdtocv       multiwire packager
16:27:50 (cdslmd) pcb_editor pcb_engineer pcb_interactive
16:27:50 (cdslmd) pcb_prep pcb_review pcomp
16:27:50 (cdslmd) placement plotVersa ptc_in
16:27:50 (cdslmd) ptc_out       quanticout redifnet
16:27:50 (cdslmd) rt       sdrc_in       sdrc_out
16:27:50 (cdslmd) signoise skillDev stream_in
16:27:50 (cdslmd) stream_out swap       sx
16:27:50 (cdslmd) synSmartIF synSmartLib synTiOpt
16:27:50 (cdslmd) tsTSynVHDL tsTSynVLOG tsTestGen
16:27:50 (cdslmd) tsTestIntf tune       tw01
16:27:50 (cdslmd) tw02       v2e       vc-signalscan
16:27:50 (cdslmd) vc-signalscan-transaction vc-transaction-explorer verifault
16:27:50 (cdslmd) vgen       viable       visula_in
16:27:50 (cdslmd) vloglink wedifsch xilCds
16:27:50 (cdslmd) xilComposerFE xilConceptFE xilEdif
16:27:50 (cdslmd) TimingAnalysis RCExtraction DelayCal
16:27:50 (cdslmd) TrialRoute AmoebaPlace DesignViewer
16:27:50 (cdslmd) Route       CeltIC       SignalIntegrity
16:27:50 (cdslmd) ClockSyn PowerAnalysis SpecialRoute
16:27:50 (cdslmd) TimingBudget PartitionOptimizer Multithread_Route_Option
16:27:50 (cdslmd) Cierto_SPW_comm_library_fxp_pt Cierto_HW_design_sys_2000 Cierto_SPW_multimedia_kit
16:27:50 (cdslmd) Cierto_SPW_GSM_VE Cierto_SPW_IS136_VE Cierto_SPW_pcscdma_VE
16:27:50 (cdslmd) Cierto_signal_proc_wrksys_2000 Cierto_SPW_comm_lib_flt_pt SPW_Smart_Antenna_Library
16:27:50 (cdslmd) Cierto_Wireless_LAN_Library Cierto_SPW_CDMA_Library Cierto_SPW_model_manager
16:27:50 (cdslmd) Virtuoso_NeoCircuit DFM_Core_Technology Assura_DRC
16:27:50 (cdslmd) Assura_LVS Assura_MP Assura_OPC
16:27:50 (cdslmd) Assura_RCX Assura_SI-TL Assura_SI
16:27:50 (cdslmd) Assura_SiMC Assura_SiVL Assura_UI
16:27:50 (cdslmd) VoltageStorm_Cell VoltageStorm_Cell_Transistor SI_Timing_Convergence_VS
16:27:50 (cdslmd) VoltageStorm_Transistor VoltageStorm_PE STV90
16:27:50 (cdslmd) ElectronStorm_Transistor
16:27:50 (cdslmd)
16:27:50 (cdslmd) All FEATURE lines for cdslmd behave like INCREMENT lines
16:27:50 (cdslmd)
16:27:50 (cdslmd) EXTERNAL FILTERS are OFF
16:27:50 (lmgrd) cdslmd using TCP-port 32791
22:27:50 (lmgrd) TIMESTAMP 4/1/2012