A 10-bit, 100 MS/s CMOS A/D Converter(by Abidi)

semico_ljj · 发表于 2006-11-28 08:38:17

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To appear in IEEE J. of Solid-State Circuits, April 1997.

A 10-bit, 100 MS/s CMOS A/D Converter
by
K. Y. Kim, N. Kusayanagi, and A. A. Abidi
Integrated Circuits & Systems Laboratory
Electrical Engineering Department
University of California

ABSTRACT
A new architecture for a CMOS A/D converter overcomes many of the
known problems in the parallel operation of multiple pipelined stages. The
input signal is sampled in one channel, and after quantization to 4 bits, the
residue is distributed into many channels. A prototype implemented in 1µm
CMOS achieves 60 dB SNDR at low conversion rates, with a resolution
bandwidth of greater than 20 MHz. The SNDR drops by 3 dB at a 95 MHz
conversion rate, and the bandwidth remains the same.

semico_ljj · 发表于 2006-11-28 09:11:44

配套详细Slides 78页

Outline
I. Introduction
II. High Speed A/D Converter Architectures
III. Proposed A/D Converter Architecture
IV. Circuit Design and Simulations
V. Layout
VI. Prototype Chip Test Results
VII. Conclusion

[ 本帖最后由 semico_ljj 于 2006-11-28 09:14 编辑 ]

semico_ljj · 发表于 2006-11-28 09:12:56

A 10-bit, 100 MHz CMOS
Analog-to-Digital Converter
Kwang Young Kim, N. Kusayanagi, and A. A. Abidi
Integrated Circuits and Systems Laboratory
Electrical Engineering Department
University of California, Los Angeles