Think clearly, before you adopt UVM

唐龙

I'm glad that nowadays SystemVerilog and UVM are most popular things engineers are concerned. But does everyone really think things clearly before adopt them? I think maybe not.
    Generally speaking, there is not the best ones. All the verification methodologies are developed by simulator suppliers and verification languages and are commercial. They just compete with each other to earn more marketplaces. But the fierce compete leads to progress of the whole EDA industry, there do have step a big forward. Say, it much like weapons, are you sure the more complicated ones can beat all enemies？the answer maybe no. The more complicated the more difficult to master, you have to spend much time to learn the language and methodology, also you must gain enough experience before you can use it powerfully. In my opinion, one should choose the easiest way to handle problems, the easiest is the best, not the most complicated ones. If your project is small like AVS decoder, you may not need to apply the more advanced methodologies, verilog is just enough to deal all things, maybe some other verification languages also will do,such as E,Vera.If your project really very big, such as smart phones SOC etc. verilog is inefficient to take charge in, then, you may think of more advanced methodologies, such as OVM, VMM, UVM. they will make verification easier. the other choice when one face to SOC era, one may use the powerful SystemC as a system model and verification tools. the more abstract the more one can improve their productivity and efficiency.


     Welcome everyone to participate in discussing this topic.

飞扬紫百合

Every Methodology has its own advantages! Chosing the most adaptive PL according to your EDA suite is very important!

太阳公子

不会中国字么，拽什么洋文。在中文论坛装什么

唐龙

回复 3# 太阳公子


   Are you stupid or something? Why don't you programming in Chinese? If you don't have a good command of English, you cannot be a good IC designer.

arronsun

Methodology is just a tool which can make verification easier and can greatly ruduce our effort.
I am currently engaged in verification using OVM. According to my experience, not all project is suitable to use OVM.
All profite advance methodology brings to us are based on constrainted random generation.
Personal opinion,OVM just facilitate transactions travel from souce to destination
,the foundation and also the most important is transaction based verification, OVM is just a tool to help us achieve our goal easier.

welcome discussing

楚逐浪

楼主讲的很有道理，不过我感觉还是要学一下，搞技术总是要上进的不是。

moonlightbrothe

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oceanyt

嗯 不错 可以讨论讨论！