[资料] 2011年9月JSSC
IEEE Journal Of Solid State Circuits
题目为
1、Four Channel, 40 ps Resolution, Fully Integrated Time-to-Amplitude Converter for Time-Resolved Photon Counting
2、A 1.25 ps Resolution 8b Cyclic TDC in 0.13 m CMOS
3、A Pulse Shaping Technique for Spur Suppression in Injection-Locked Synthesizers
4、Power and Area Minimization of Reconfigurable FFT Processors: A 3GPP-LTE Example
5、A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology
6、A Fully Integrated, 290 pJ/bit UWB Dual-Mode Transceiver for cm-Range Wireless Interconnects
7、A 3x9 Gb/s Shared, All-Digital CDR for High-Speed, High-Density I/O
8、A 1 W 104 dB SNR Filter-Less Fully-Digital Open-Loop Class D Audio Amplifier With EMI Reduction
9、A Low-Power Magnitude Detector for Analysis of Transient-Rich Signals
10、A 1.9–3.8 GHz Fractional-N PLL Frequency Synthesizer With Fast Auto-Calibration of Loop Bandwidth and VCO Frequency
11、A 250 mV 7.5 μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS
12、A Fully-Integrated High-Power Linear CMOS Power Amplifier With a Parallel-Series Combining Transformer
13、Synchronous-Logic and Globally-Asynchronous-Locally-Synchronous (GALS) Acoustic Digital Signal Processors
14、Design and Analysis of a Hardware-Efficient Compressed Sensing Architecture for Data Compression in Wireless Sensors
15、A 40-Gb/s Optical Transceiver Front-End in 45 nm SOI CMOS
16、A 0.5-V 35- W 85-dB DR Double-Sampled Modulator for Audio Applications
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发表于 2012-3-24 00:50:43
发表于 2012-3-24 10:48:13
