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查看: 14958|回复: 19

[求助] DC综合问题

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发表于 2012-3-21 14:53:31 | 显示全部楼层 |阅读模式

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x
代码很简单
module mul(a,b,c);
  input [5:0]a;
  input [5:0]b;
  output [10:0]c;
   reg  [10:0]c;

always @(posedge clk)
   begin
       if(!rst_n)
            begin
                c<=0;
            end
       else
            begin
                  c <= a*b;
           end
    end
endmodule


然后综合结果显示Warning: In design 'Lens_mul', cell 'B_2' does not drive any nets.
Warning: Module Lens_mul contains unmapped components.  The output netlist might not be read back into the system.


没有error,但是面积报告上都是0,请问是什么情况
 楼主| 发表于 2012-3-21 14:54:53 | 显示全部楼层
求解答啊
 楼主| 发表于 2012-3-21 15:00:50 | 显示全部楼层
有人来没有
 楼主| 发表于 2012-3-21 16:09:24 | 显示全部楼层
Warning: In design 'Lens_mul_DW02_mult_0', the same net is connected to more than one pin on submodule 'FS_1'. (LINT-33)
   Net 'n3' is connected to pins 'B[3]', 'B[2]', 'B[1]'.
   Net '*Logic0*' is connected to pins 'B[0]', 'CI'.
Warning: In design 'Lens_mul_DW01_add_0', port 'A[9]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[4]' is connected directly to output port 'SUM[4]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[3]' is connected directly to output port 'SUM[3]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[2]' is connected directly to output port 'SUM[2]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[1]' is connected directly to output port 'SUM[1]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', input port 'A[0]' is connected directly to output port 'SUM[0]'. (LINT-29)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[9]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[4]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[3]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[2]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[1]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'B[0]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'CI' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'SUM[9]' is not connected to any nets. (LINT-28)
Warning: In design 'Lens_mul_DW01_add_0', port 'CO' is not connected to any nets. (LINT-28)

还有这些warning 需要关注么
发表于 2012-3-21 16:30:47 | 显示全部楼层
IO list里面没有clk和rst_n!
发表于 2012-3-21 16:31:58 | 显示全部楼层
回复 1# zxxqs


   建议你先把仿真弄通过了,再来综合。
 楼主| 发表于 2012-3-21 16:54:56 | 显示全部楼层
回复 6# keelinx


    额 发帖子的时候忘记写了 我的代码已经仿真通过的 有clk和rst_n的
发表于 2012-3-21 17:19:50 | 显示全部楼层
或许把乘法器模块代码,乘法器例化代码,相关log截个图发上来会比较容易分析~~
发表于 2012-3-22 23:19:56 | 显示全部楼层
你有读入design ware库玛?
发表于 2012-4-12 10:44:12 | 显示全部楼层
两个错误,纠正如下:
1. always @(posedge clk or negedge rst_n)
2. a[5:0] b[5:0]两个相乘c应该定义成reg [11:0] c;
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