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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity seris_gen is
generic(n : NATURAL := 3);
port(clk : in std_logic;
reset: in std_logic;
q : out std_logic;
end seris_gen;
architecture behave of seris_gen is
signal q_n: std_logic_vector(3 downto 0);
begin
p0: process (clk, reset) is
variable cnt : unsigned(n-1 downto 0);
begin
if reset = '1' then
cnt := (others => '0');
elsif rising_edge(clk) then
cnt := cnt + 1;
end if
end process p0;
p1: process(clk, reset, cnt, q_n) is
begin
if (reset = '1') then
q_n <= '1';
elsif rising_edge(clk) then
if (cnt[2] and cnt[1]) = '1' then
q_n <= '0';
else
q_n <= '1';
end if;
end if;
end process p1;
q <= q_n;
end behave; |
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