Nvidia英伟达 上海 职位

annabelliu

Position Title:	if you are interested in,please contact  annabell@nvidia.com    circuit design engineer
Description/ Qualifications:	RESPONSIBILITIES: - High performance, low power custom digital circuit design for graphics processors. - Circuit architecting, simulation and characterization of custom design circuit. - Logic equivalence checking and transistor level function verification. - Participating in building CAD flow for circuit design. - Layout floor planning and supervision. MINIMUM REQUIREMENTS: - BSEE minimum, MSEE preferred. - Strong background in deep submicron CMOS process and device. - Good knowledge in high speed digital circuit design techniques. - Understanding of on-chip inter connect and signal integrity. - Experience in circuit simulation, schematic capture and layout verification CAD tools. - Must be a team player with effective written and verbal communication skills. - Must be able to learn quickly and work independently.- Experience in SRAM/ROM design is preferred. - 1~3 years working experience is preferred

GPU ASIC Physical Design engineer

As a senior member of our ASIC-PD team, you'll be working on streamlining the chip infrastructure process across product designs, focusing on full chip layout planning (partitioning, planning clock distribution and other structure, methodology), partition/full chip timing closure (primetime scripts, other tools, etc) and gate-level design of high-speed logic

RESPONSIBILITIES:

- Chip integration and netlist generation

-Synthesis, Formal verification, netlist quality check

- Work in conjunction with Place and Route Engineers to achieve timing closure for both partition level and full chip level
- Develop and enhance entire timing flow from frontend (pre-layout) to backend (post-layout) at both chip and block level.
- Develop custom timing scripts using tcl/primetime for clock skew analysis, special circuits such as clock dividers, core logic <-> IO macros interfaces such as PCI-E, Frame-Buffer/Memory, TMDS, etc.
- Develop flow to physically partition and floorplan the entire chip.
- Develop scripts for performing ECO's.

MINIMUM REQUIREMENTS:
- BS or MS in Electrical Engineering or Computer Science
- Above 3 years of relevant ASIC experience ideally with a focus in the chip integration /synthesis/formal and timing closure

- Excellent scripts skills

- Excellent written and verbal communication skills in English

- Ability to multiplex many issues, set priorities, and work in a team environment

- Keep up to date with leading edge technologies

SR. PHYSICAL DESIGN METHODOLOGY ENGINEER

RESPONSIBILITIES:
- Responsible for the development of the physical design methodologies and flow automation for large and high speed semicustom chips using deep submicron processes. This includes evaluating and helping improve third party tools, developing internal tools and solutions, and supporting the physical design implementation team.

MINIMUM REQUIREMENTS:
- BSEE or BSCS
- 3+ years
of experience in large VLSI physical design implementation and automation and methodology.

- Strong experience in programming of one of the following area: C/C++, Perl, Python.

- Prior experience in timing closure, CTS, power distribution and analysis, power efficiency, RC extraction and correlation, xtalk analysis, signal EM,

   place and route, DRC/LVS and tapeout issues.
- Working knowledge of deep sub-micron issues.
- Should be a power user of P&R and timing analysis CAD tools from Magma (Blast, Talus), Synopsys (ICC/DC/PT/STAR-RC/Astro/PC), Cadence (SOCE),  Mentor Graphics (Pinnacle/Olympus) or Atoptech.
- Proficiency using Perl, TCL, Make scripting.

- Knowledge/Proficiency of C/C++ or any other software language is a plus.

- Experience at 40nm and 28nm is a plus.

- Circuit level comprehension of time critical paths and Spice experience are a plus.

1.
PHYSICAL DESIGN ENGINEER

RESPONSIBILITIES:
- Responsible for all aspects of physical design and implementation of Graphics processors, Mobile CPU and other ASICs targeted at the desktop, laptop, workstation, set-top box, tablet, smart phone and home networking markets
- Participating in the efforts in establishing CAD and physical design methodologies, flow automation, chip floorplan, power/clock distribution, chip assembly and P&R, timing closure
- Working on static timing analysis, power and noise analysis and back-end verification across multiple projects

MINIMUM REQUIREMENTS:
- BSEE, MSEE preferred
- Experience in large VLSI physical design implementation on 0.18u, 0.13u, 90nm, or 65nm technology
- Successful track record of delivering products to production is a must.
- Understanding of custom macro blocks such as RAMs, CAMs, high-speed IO drivers
- Prior experience in Timing closure, clock/power Distribution and analysis, RC Extraction and correlation, place and route and tapeout issues
- Working knowledge of deep sub-micron routing issues as they relate to power and timing
- Circuit level comprehension of time critical paths, and spice experience a plus
- Should be a power user of P&R and timing analysis CAD tools from Synopsys (ICC/Astro/PC/dc_shell/pt_shell/STAR-RC), Cadence (FE/Nanoroute), Mentor (Pinnacle) or Magma
- Proficiency using Perl, TCL, Scheme, Make scripting is preferred

annabell@nvidia.com

angelaqina

顶一个。