Cadence 招聘Lead product Valication Enginner & Senior product Engineer

kengteng

If you have interest,PLS send your CV to job_china@cadence.com

PE

1. Senior Product Engineer for QoS(Location: SH)

Position Description

1.This job is an important addition to Encounter quality and performance

2.Responsible for QOS analysis and debug for EDI whole backend flow, from floorplan to final SI timing closure

3.Responsible for CPU and memory qualify maintain during regular review

4.Continuously to add and tune large scale and advance node designs into QoS suite

5.Working closely with other team members for technique communication and projects. Can take lead role in project plan and action.

Position Requirements

1.BS with minimum 5 years and MS with 3 years working experiences. EE background, previous experience on EDA tools and frontend/backend design is a strong plusExcellent knowledge at backend flow in digital design, including placement, optimization, cts, route and SI, which is the most important for this job.

2.Excellent knowledge at timing analysis, good at power analysis and low power.

3.Be familiar with software development process, debugging tools, and configuration management concepts.

4.Know well about verilog, simulation, dft, dfm.

5.Excellent ability to learn, explore and strong ability in solving problems independently.

6.Good team working attitude and innovating spirit.

7.Good Chinese and English communication skills.

2.Senior Product Engineer for LP QoS

Position Description

This employee will work in shanghai QoS(Quality Of Silicon) team, mainly focus on the LowPower QoS, including :

1.Tune customer LP cases and added them in a QoS way.

2.QOS analysis and debug for EDI whole backend LP flow, from floorplan to final SI timing closure

3.Work closely with other team members for technique communication and projects. Can take lead role in project plan and action.

4.Co-work closely with R&D team to find the debug the software problem in a IC backend way as early as possible.

Position Description

1.Master with 3-4 years working experience or Bachelor with 6-7 years experience.

2.IC design background, especially in the back-end flow. Low Power related working experience will be a strong plus.

3.Unix System knowledge, vi/TCL/TK/CSH will be plus.

4.Strong scripting capability, including shell/tcl/perl.

5.Good communication in English and Chinese, good confidence and good self-motivation.

6.Good team spirit, well-aligned with the "One Cadence, One Team."

PV

1.
Principal PV Project Lead(Location: SH)

Position Description:

1.This job is an important addition to Encounter quality and performance

2.Responsible for QOR analysis and debug for EDI whole backend flow(后端流程), from placement to final SI timing closure

3.Responsible for CPU and memory qualify maintain during regular review

4.Continuously to add and tune large scale and advance node designs into validation suite

5.Working closely with other team members for technique communication and projects. Can take lead role in project plan and action.

Position Requirements:

1.BS with minimum 6 years and MS with 5 years working experiences. EE background, from design house or EDA company is strong plus.

2.Be familiar with software development process, debugging tools, and configuration management concepts.

3.Excellent knowledge at backend flow in digital design, including placement, optimization, cts, route and SI, which is the most important for this job.

4.Excellent knowledge at timing analysis, good at power analysis and low power.

5.Know well about verilog, simulation, dft, dfm.

6.Excellent ability to learn, explore and strong ability in solving problems independently.

7.Good team working attitude and innovating spirit.

8.Good Chinese and English communication skills.

2. Lead PV Engineer for QOR(Location: SH)

Position Description:

1.Run QOR regression on multiple design suites daily and weekly to catch QOR/Performance issues in time, debug and file bugs to RD for QOR degradations.

2.Take projects from RD or PE requests in validating code changes.

3.Add and tune designs into current suite, including advance technology designs and larger designs.

4.Develop system using scripts such as cshell, perl or tcl.

Position Requirements:

1.BS with 4 years or MS 2years of EE background, from design house or EDA Company or fab is strong plus.

2.Know good at APR flow, such as placement, route, cts, optimization, xtalk etc.

3.Be familiar with software development process, debugging tools, and configuration management concepts.

4.Candidate must have excellent ability to learn, explore and solve problems, have team-cooperating and innovating spirit,

5.Candidate must possess good Chinese and English communication skills;